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? 2009-2013 microchip technology inc. ds60001156h-page 1 pic32mx5xx/6xx/7xx operating conditions ? 2.3v to 3.6v, -40oc to +105oc, dc to 80 mhz core: 80 mhz/105 dmips mips32 ? m4k ? ? mips16e ? mode for up to 40% smaller code size ? code-efficient (c and assembly) architecture ? single-cycle (mac) 32x16 and two-cycle 32x32 multiply clock management ? 0.9% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer ? fast wake-up and start-up power management ? low-power management modes (sleep and idle) ? integrated power-on reset, brown-out reset ? 0.5 ma/mhz dynamic current (typical) ? 41 a ipd current (typical) graphics features ? external graphics interface with up to 34 parallel master port (pmp) pins: - interface to external graphics controller - capable of driving lcd directly with dma and internal or external memory analog features ? adc module: - 10-bit 1 msps rate with one sample and hold (s&h) - 16 analog inputs - can operate during sleep mode ? flexible and independent adc trigger sources ?comparators: - two dual-input comparator modules - programmable references with 32 voltage points timers/output compare/input capture ? five general purpose timers: - five 16-bit and up to two 32-bit timers/counters ? five output compare (oc) modules ? five input capture (ic) modules ? real-time clock and calendar (rtcc) module communication interfaces ? usb 2.0-compliant full-speed otg controller ? 10/100 mbps ethernet mac with mii and rmii interface ? can module: - 2.0b active with devicenet? addressing support ? six uart modules (20 mbps): - supports lin 1.2 protocols and irda ? support ? up to four 4-wire spi modules (25 mbps) ? up to five i 2 c modules (up to 1 mbaud) with smbus support ? parallel master port (pmp) direct memory access (dma) ? up to eight channels of hardware dma with automatic data size detection ? 32-bit programmable cyclic redundancy check (crc) ? six additional channels dedicated to usb, ethernet and can modules input/output ? 15 ma or 10 ma source/sink for standard v oh /v ol and up to 22 ma for non-standard v oh 1 ? 5v-tolerant pins ? selectable open drain and pull-ups ? external interrupts qualification and class b support ? aec-q100 revg (grade 2 -40oc to +105oc) planned ? class b safety library, iec 60730 debugger development support ? in-circuit and in-application programming ?4-wire mips ? enhanced jtag interface ? unlimited program and six complex data breakpoints ? ieee 1149.2-compatible (jtag) boundary scan packages type qfn tqfp tfbga vtla pin count 64 64 100 100 121 124 i/o pins (up to) 51 51 83 83 83 83 contact/lead pitch 0.50 0.50 0.40 0.50 0.80 0.50 dimensions 9x9x0.9 10x10x1 12x12x1 14 x14x1 10x10x1.1 9x9x0.9 note: all dimensions are in millimeters (mm) unless specified. 32-bit microcontrollers (up to 512 kb flash and 128 kb sram) with graphics interface, usb, can, and ethernet
pic32mx5xx/6xx/7xx ds60001156h-page 2 ? 2009-2013 microchip technology inc. table 1: pic32 usb and can ? features usb and can device pins program memory (kb) data memory (kb) usb can timers/capture/compare dma channels (programmable/dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx534f064h 64 64 + 12 (1) 16 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx564f064h 64 64 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx564f128h 64 128 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx575f256h 64 256 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx575f512h 64 512 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx534f064l 100 64 + 12 (1) 16 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx564f064l 100 64 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx564f128l 100 128 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx575f256l 100 256 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx575f512l 100 512 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg legend: pf, pt = tqfp mr = qfn bg = tfbga tl = vtla (5) note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section33.0 ?packaging information? for more information. 5: 100-pin devices in the vtla package are available upon request. please contact your local microchip sales office for details.
? 2009-2013 microchip technology inc. ds60001156h-page 3 pic32mx5xx/6xx/7xx table 2: pic32 usb and ethernet ? features usb and ethernet device pins program memory (kb) data memory (kb) usb ethernet timers/capture/compare dma channels (programmable/dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx664f064h 64 64 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx664f128h 64 128 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx675f256h 64 256 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx675f512h 64 512 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx695f512h 64 512 + 12 (1) 128 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx664f064l 100 64 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx664f128l 100 128 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx675f256l 100 256 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx675f512l 100 512 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg, tl pic32mx695f512l 100 512 + 12 (1) 128 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg, tl legend: pf, pt = tqfp mr = qfn bg = tfbga tl = vtla (5) note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section33.0 ?packaging information? for more information. 5: 100-pin devices other than those listed here are available in the vtla pack age upon request. please contact your local microchip sales office for details.
pic32mx5xx/6xx/7xx ds60001156h-page 4 ? 2009-2013 microchip technology inc. table 3: pic32 usb, ethernet and can ? features usb, ethernet and can device pins program memory (kb) data memory (kb) usb ethernet can timers/capture/compare dma channels (programmable/dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx764f128h 64 128 + 12 (1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 yes yes no pt, mr pic32mx775f256h 64 256 + 12 (1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr pic32mx775f512h 64 512 + 12 (1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr pic32mx795f512h 64 512 + 12 (1) 128 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr PIC32MX764F128L 100 128 + 12 (1) 32 1 1 1 5/5/5 4/6 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx775f256l 100 256 + 12 (1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx775f512l 100 512 + 12 (1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx795f512l 100 512 + 12 (1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg, tl legend: pf, pt = tqfp mr = qfn bg = tfbga tl = vtla (5) note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section 33.0 ?packaging information? for more information. 5: 100-pin devices other than those listed here are available in the vtla package upon request. please contact your local microchip sales office for details.
? 2009-2013 microchip technology inc. ds60001156h-page 5 pic32mx5xx/6xx/7xx pin diagrams 64-pin qfn (1) = pins are up to 5v tolerant note 1: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. pic32mx575f256h pmd5/re5 pmd6/re6 pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/ocfb/pmall/pma0/cn12/rb15 v ss av ss cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 sck3/u4tx/u1rts /oc2/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 c1rx/rf0 v cap pmd0/re0 c1tx/rf1 cn16/rd7 v dd sosci/cn1/rc13 oc1/int0/rd0 scl1/ic3/pmcs2/pma15/int3/rd10 ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/ic1/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx575f512h pic32mx534f064h pic32mx564f064h pic32mx564f128h
pic32mx5xx/6xx/7xx ds60001156h-page 6 ? 2009-2013 microchip technology inc. pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant pic32mx675f512h pic32mx695f512h pic32mx675f256h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rtsu2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally. pic32mx664f064h pic32mx664f128h
? 2009-2013 microchip technology inc. ds60001156h-page 7 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclkpmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd pic32mx795f512h pic32mx775f256h pic32mx775f512h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/c2tx/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/c2rx/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally.
pic32mx5xx/6xx/7xx ds60001156h-page 8 ? 2009-2013 microchip technology inc. pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclkpmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd pic32mx764f128h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally.
? 2009-2013 microchip technology inc. ds60001156h-page 9 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx575f256h pmd5/re5 pmd6/re6 pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/ocfb/pmall/pma0/cn12/rb15 v ss av ss cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 sck3/u4tx/u1rts /oc2/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 c1rx/rf0 v cap pmd0/re0 c1tx/rf1 cn16/rd7 v dd sosci/cn1/rc13 oc1/int0/rd0 scl1/ic3/pmcs2/pm a15/int3/rd10 ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/ic1/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx575f512h pic32mx534f064h pic32mx564f064h pic32mx564f128h
pic32mx5xx/6xx/7xx ds60001156h-page 10 ? 2009-2013 microchip technology inc. pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx675f512h pic32mx695f512h pic32mx675f256h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx664f064h pic32mx664f128h
? 2009-2013 microchip technology inc. ds60001156h-page 11 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx795f512h pic32mx775f256h pic32mx775f512h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/c2tx/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/c2rx/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss
pic32mx5xx/6xx/7xx ds60001156h-page 12 ? 2009-2013 microchip technology inc. pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx764f128h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rxu1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss
? 2009-2013 microchip technology inc. ds60001156h-page 13 pic32mx5xx/6xx/7xx pin diagrams (continued) pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 pmd13/cn19/rd13 ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/pmd11/rf0 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2/rd9 rtcc/ic1/rd8 ic4/pmcs1/pma14/rd11 sda1/int4/ra15 scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/pma6/ra10 v ref -/cv ref -/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 ss3 /u4rx/u1cts /cn20/rd14 sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 int1/re8 int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd rg15 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr an12/pma11/rb12 an13/pma10/rb13 an14/pmalh/pma1/rb14 an15/ocfb/pmall/pma0/cn12/rb15 pmd9/rg1 c1tx/pmd10/rf1 v dd pmd14/cn15/rd6 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss v ss v cap tdi/ra4 tck/ra1 100-pin tqfp pmd15/cn16/rd7 = pins are up to 5v tolerant 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 1 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 27 46 47 48 49 55 54 53 52 51 50 26 pic32mx575f512l 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 pic32mx575f256l pic32mx534f064l pic32mx564f064l pic32mx564f128l
pic32mx5xx/6xx/7xx ds60001156h-page 14 ? 2009-2013 microchip technology inc. pin diagrams (continued) 100-pin tqfp pic32mx675f512l pic32mx695f512l pic32mx675f256l = pins are up to 5v tolerant pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr etxerr/pmd9/rg1 etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 ss1/ ic2/rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd11 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ss4 /u5rx/u2cts /rf12 sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 sck1/ic3/pmcs2/pma15/rd10 pic32mx664f064l pic32mx664f128l pgec2/an6/ocfa/rb6 26
? 2009-2013 microchip technology inc. ds60001156h-page 15 pic32mx5xx/6xx/7xx pin diagrams (continued) 100-pin tqfp = pins are up to 5v tolerant pic32mx795f512l pic32mx775f256l pic32mx775f512l pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 c2rx/pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/ac2tx/rc2 t4ck/ac2rx/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr c2tx/etxerr/pmd9/rg1 c1tx/etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2 / rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd1 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 26
pic32mx5xx/6xx/7xx ds60001156h-page 16 ? 2009-2013 microchip technology inc. pin diagrams (continued) 100-pin tqfp = pins are up to 5v tolerant PIC32MX764F128L pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr etxerr/pmd9/rg1 c1tx/etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2 / rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd1 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb 3 v 3 v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 26
? 2009-2013 microchip technology inc. ds60001156h-page 17 pic32mx5xx/6xx/7xx pin diagrams (continued) 121-pin tfbga (1) 1234567891011 a re4 re3 rg13 re0 rg0 rf1 v dd v ss rd12 rd2 rd1 b nc rg15 re2 re1 ra7 rf0 v cap rd5 rd3 v ss rc14 c re6 v dd rg12 rg14 ra6 nc rd7 rd4 v dd rc13 rd11 d rc1 re7 re5 v ss v ss nc rd6 rd13 rd0 nc rd10 e rc4 rc3 rg6 rc2 v dd rg1 v ss ra15 rd8 rd9 ra14 f mclr rg8 rg9 rg7 v ss nc nc v dd rc12 v ss rc15 g re8 re9 ra0 nc v dd v ss v ss nc ra5 ra3 ra4 h rb5 rb4 v ss v dd nc v dd nc v bus v usb 3 v 3 rg2 ra2 j rb3 rb2 rb7 av dd rb11 ra1 rb12 nc nc rf8 rg3 k rb1 rb0 ra10 rb8 nc rf12 rb14 v dd rd15 rf3 rf2 l rb6 ra9 av ss rb9 rb10 rf13 rb13 rb15 rd14 rf4 rf5 pic32mx575f256l note 1: refer to table 4 , ta b l e 5 and ta b l e 6 for full pin names. = pins are up to 5v tolerant pic32mx795f512l pic32mx575f512l pic32mx675f512l pic32mx695f512l pic32mx675f256l pic32mx775f256l pic32mx775f512l pic32mx534f064l pic32mx564f064l pic32mx564f128l pic32mx664f064l pic32mx664f128l PIC32MX764F128L
pic32mx5xx/6xx/7xx ds60001156h-page 18 ? 2009-2013 microchip technology inc. table 4: pin names: pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pi c32mx575f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 c1tx/pmd10/rf1 f2 scl4/sdo2/u3tx/pma3/cn10/rg8 a7 v dd f3 ss2 /u6rx/u3cts /pma2/cn11/rg9 a8 v ss f4 sda4/sdi2/u3rx/pma4/cn9/rg7 a9 ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 int1/re8 b6 c1rx/pmd11/rf0 g2 int2/re9 b7 v cap g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb 3 v 3 d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 sck2/u6txu6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/pma6/ra10
? 2009-2013 microchip technology inc. ds60001156h-page 19 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/pma10/rb13 k9 sck3/u4tx/u1rts /cn21/rd15 l8 an15/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/pma7/ra9 table 4: pin names: pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pic32mx575 f512l devices (continued) pin number full pin name pin number full pin name
pic32mx5xx/6xx/7xx ds60001156h-page 20 ? 2009-2013 microchip technology inc. table 5: pin names: pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/emdio/aemdio/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 etxd0/pmd10/rf1 f2 erxdv/aerxdv/ecrsdv/aecrsdv//scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb 3 v 3 d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11/erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10
? 2009-2013 microchip technology inc. ds60001156h-page 21 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 5: pin names: pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices (continued) pin number full pin name pin number full pin name
pic32mx5xx/6xx/7xx ds60001156h-page 22 ? 2009-2013 microchip technology inc. table 6: pin names: pic32m x775f256l, pic32mx775f512l and pic32mx795f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/em dio/aemdi o/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 c2rx/pmd8/rg0 f1 mclr a6 c1tx/etxd0/pmd10/rf1 f2 erxdv/aer xdv/ecrsdv/aecrsdv/scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 c1rx/etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb 3 v 3 d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11 /erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/ac2rx/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/ac2tx/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 c2tx/etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10
? 2009-2013 microchip technology inc. ds60001156h-page 23 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 6: pin names: pic32m x775f256l, pic32mx775f512l and pic32mx795f512l devices (continued) pin number full pin name pin number full pin name
pic32mx5xx/6xx/7xx ds60001156h-page 24 ? 2009-2013 microchip technology inc. table 7: pin name: pi c32mx764f128l device pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/em dio/aemdi o/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 c1tx/etxd0/pmd10/rf1 f2 erxdv/aer xdv/ecrsdv/aecrsdv/scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 c1rx/etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb 3 v 3 d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11 /erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10
? 2009-2013 microchip technology inc. ds60001156h-page 25 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 7: pin name: pic32mx7 64f128l device (continued) pin number full pin name pin number full pin name
pic32mx5xx/6xx/7xx ds60001156h-page 26 ? 2009-2013 microchip technology inc. pin diagrams (continued) 124-pin vtla (1) = pins are up to 5v tolerant note 1: refer to ta b l e 8 for the full li st of pin names. a68 a67 a66 a65 a64 a63 a62 a61 a60 a59 a58 a57 a56 a55 a54 a53 a52 a51 a1 b56 b55 b54 b53 b52 b51 b50 b49 b48 b47 b46 b45 b44 b43 b42 a50 a2 b1 a49 a16 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 a35 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 a32 a33 a34 a3 b2 b41 a48 a4 b3 b40 a47 a5 b4 b39 a46 a6 b5 b38 a45 a7 b6 b37 a44 a8 b7 b36 a43 a10 b9 b34 a41 a11 b10 b33 a40 a12 b11 b32 a39 a13 b12 b31 a38 a14 b13 b30 a37 a15 b29 a36 a9 b8 b35 a42 pic32mx675f512l pic32mx695f512l b32 b31 b30 pic32mx795f512l
? 2009-2013 microchip technology inc. ds60001156h-page 27 pic32mx5xx/6xx/7xx table 8: pin names: pic32mx6 75f512l, pic32mx6 95f512l, and pic32mx 795f512l devices package bump # full pin name package bump # full pin name a1 no connect (nc) a52 oc2/rd1 a2 aerxerr/rg15 a53 oc4/rd3 a3 v ss a54 etxd3/pmd13/cn19/rd13 a4 pmd6/re6 a55 pmrd/cn14/rd5 a5 t2ck/rc1 a56 etxclk/pmd15/cn16/rd7 a6 t4ck/ac2rx (1) /rc3 a57 no connect (nc) a7 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 a58 no connect (nc) a8 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/ u3tx/pma3/cn10/rg8 a59 v dd a9 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts/pma2/cn11/rg9 a60 c1tx (1) /etxd0/pmd10/rf1 a10 v dd a61 c2rx (1) /pmd8/rg0 a11 aerxd0/int1/re8 a62 trd3/ra7 a12 an5/c1in+/vbuson/cn7/rb5 a63 v ss a13 an3/c2in+/cn5/rb3 a64 pmd1/re1 a14 v dd a65 trd1/rg12 a15 pgec1/an1/cn3/rb1 a66 pmd2/re2 a16 no connect (nc) a67 pmd4/re4 a17 no connect (nc) a68 no connect (nc) a18 no connect (nc) b1 v dd a19 no connect (nc) b2 pmd5/re5 a20 pgec2/an6/ocfa/rb6 b3 pmd7/re7 a21 v ref -/cv ref -/aerxd2/pma7/ra9 b4 t3ck/ac2tx/rc2 a22 av dd b5 t5ck/sdi1/rc4 a23 an8/c1out/rb8 b6 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a24 an10/cv refout /pma13/rb10 b7 mclr a25 v ss b8 v ss a26 tck/ra1 b9 tms/ra0 a27 ac1rx (1) /ss4 /u5rx/u2cts /rf12 b10 aerxd1/int2/re9 a28 an13/erxd1/aecol/pma10/rb13 b11 an4/c1in-/cn6/rb4 a29 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 b12 v ss a30 v dd b13 an2/c2in-/cn4/rb2 a31 aetxd1/sck3/u4tx/u1rts /cn21/rd15 b14 pged1/an0/cn2/rb0 a32 scl5/sdo4/u2tx/pma8/cn1 8/rf5 b15 no connect (nc) a33 no connect (nc) b16 pged2/an7/rb7 a34 no connect (nc) b17 v ref +/cv ref +/aerxd3/pma6/ra10 a35 usbid/rf3 b18 av ss a36 sda3/sdi3/u1rx/rf2 b19 an9/c2out/rb9 a37 vbus b20 an11/erxerr/aetxerr/pma12/rb11 a38 d-/rg3 b21 v dd a39 scl2/ra2 b22 ac1tx (1) /sck4/u5tx/u2rts /rf13 a40 tdi/ra4 b23 an12/erxd0/aecrs/pma11/rb12 a41 v dd b24 an14/erxd2/aetxd3/pmalh/pma1/rb14 a42 osc2/clko/rc15 b25 v ss a43 v ss b26 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 a44 aetxen/sda1/int4/ra15 b27 sda5/sdi4/u2rx/pma9/cn17/rf4 a45 ss1 /ic2/rd9 b28 no connect (nc) a46 emdc/aemdc/ic4/pmcs1/pma14/rd11 b29 scl3/sdo3/u1tx/rf8 a47 sosci/cn1/rc13 b30 v usb 3 v 3 a48 v dd b31 d+/rg2 a49 no connect (nc) b32 sda2/ra3 a50 no connect (nc) b33 tdo/ra5 a51 no connect (nc) b34 osc1/clki/rc12 note 1: this pin is only availabl e on pic32mx795f512l devices.
pic32mx5xx/6xx/7xx ds60001156h-page 28 ? 2009-2013 microchip technology inc. b35 no connect (nc) b46 v ss b36 aetxclk/scl1/int3/ra14 b47 no connect (nc) b37 rtcc/emdio/aemdio/ic1/rd8 b48 v cap b38 sck1/ic3/pmcs2/pma15/rd10 b49 c1rx/etxd1/pmd11/rf0 b39 sdo1/oc1/int0/rd0 b50 c2tx/etxerr/pmd9/rg1 b40 sosco/t1ck/cn0/rc14 b51 trclk/ra6 b41 v ss b52 pmd0/re0 b42 oc3/rd2 b53 v dd b43 etxd2/ic5/pmd12/rd12 b54 trd2/rg14 b44 oc5/pmwr/cn13/rd4 b55 trd0/rg13 b45 etxen/pmd14/cn15/rd6 b56 pmd3/re3 table 8: pin names: pic32mx6 75f512l, pic32mx6 95f512l, and pic32mx 795f512l devices package bump # full pin name package bump # full pin name note 1: this pin is only availabl e on pic32mx795f512l devices.
? 2009-2013 microchip technology inc. ds60001156h-page 29 pic32mx5xx/6xx/7xx table of contents 1.0 device overview ............................................................................................................. ........................................................... 33 2.0 guidelines for getting started with 32-bit mcus............................................................................. ........................................... 45 3.0 cpu......................................................................................................................... ................................................................... 49 4.0 memory organization ......................................................................................................... ........................................................ 55 5.0 flash program memory........................................................................................................ .................................................... 123 6.0 resets ...................................................................................................................... ................................................................ 127 7.0 interrupt controller ........................................................................................................ ........................................................... 131 8.0 oscillator configuration .................................................................................................... ........................................................ 141 9.0 prefetch cache.............................................................................................................. ........................................................... 147 10.0 direct memory access (dma) controller ...................................................................................... ........................................... 157 11.0 usb on-the-go (otg)........................................................................................................ .................................................... 173 12.0 i/o ports .................................................................................................................. ................................................................. 193 13.0 timer1 ..................................................................................................................... ................................................................. 197 14.0 timer2/3, timer4/5 ......................................................................................................... .......................................................... 201 15.0 input capture.............................................................................................................. .............................................................. 205 16.0 output compare............................................................................................................. .......................................................... 209 17.0 serial peripheral interface (spi).......................................................................................... ..................................................... 211 18.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 217 19.0 universal asynchronous receiv er transmitter (uart) ......................................................................... .................................. 223 20.0 parallel master port (pmp)................................................................................................. ...................................................... 229 21.0 real-time clock and calendar (rtcc)........................................................................................ ........................................... 237 22.0 10-bit analog-to-digital converter (adc) ................................................................................... .............................................. 247 23.0 controller area network (can) .............................................................................................. .................................................. 255 24.0 ethernet controller ........................................................................................................ ........................................................... 289 25.0 comparator ................................................................................................................. ............................................................. 331 26.0 comparator voltage reference (cv ref ) .............................................................................................................................. ... 335 27.0 power-saving features ..................................................................................................... ...................................................... 337 28.0 special features ........................................................................................................... ........................................................... 339 29.0 instruction set ............................................................................................................ .............................................................. 353 30.0 development support........................................................................................................ ....................................................... 355 31.0 electrical characteristics ................................................................................................. ......................................................... 359 32.0 dc and ac device characteristics graphs.................................................................................... .......................................... 407 33.0 packaging information...................................................................................................... ........................................................ 409 the microchip web site ......................................................................................................... ............................................................ 443 customer change notification service ........................................................................................... ................................................... 443 customer support ............................................................................................................... ............................................................... 443 reader response ................................................................................................................ .............................................................. 444 product identification system .................................................................................................. .......................................................... 445
pic32mx5xx/6xx/7xx ds60001156h-page 30 ? 2009-2013 microchip technology inc. to our valued customers it is our intention to provide our valued customers with t he best documentation possible to ensure successful use of your microchip products. to this end, we will continue to im prove our publications to bett er suit your needs. our pub- lications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this p ublication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. the last character of th e literature number is the version numbe r, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differenc es from the data sheet and recommended workarounds, may exist for current devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which devi ce, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2009-2013 microchip technology inc. ds60001156h-page 31 pic32mx5xx/6xx/7xx referenced sources this device data sheet is based on the following individual chapters of the ?pic32 family reference manual? . these documents should be considered as the general reference for t he operation of a particular module or device feature. ? section 1. ?introduction? (ds60001127) ? section 2. ?cpu? (ds60001113) ? section 4. ?prefetch cache? (ds60001119) ? section 3. ?memory organization? (ds60001115) ? section 5. ?flash program memory? (ds60001121) ? section 6. ?oscillator configuration? (ds60001112) ? section 7. ?resets? (ds60001118) ? section 8. ?interrupt controller? (ds60001108) ? section 9. ?watchdog timer and power-up timer (ds60001114) ? section 10. ?power-saving features? (ds60001130) ? section 12. ?i/o ports? (ds60001120) ? section 13. ?parallel master port (pmp)? (ds60001128) ? section 14. ?timers? (ds60001105) ? section 15. ?input capture? (ds60001122) ? section 16. ?output capture? (ds60001111) ? section 17. ?10-bit analog-to -digital converter (adc)? (ds60001104) ? section 19. ?comparator? (ds60001110) ? section 20. ?comparator voltage reference (cv ref )? (ds60001109) ? section 21. ?universal asynchronous receiver transmitter (uart)? (ds60001107) ? section 23. ?serial peri pheral interface (spi)? (ds60001106) ? section 24. ?inter-integ rated circuit (i2c?)? (ds60001116) ? section 27. ?usb on-the-go (otg)? (ds60001126) ? section 29. ?real-time clock and calendar (rtcc)? (ds60001125) ? section 31. ?direct memory access (dma) controller? (ds60001117) ? section 32. ?configuration? (ds60001124) ? section 33. ?programming and diagnostics? (ds60001129) ? section 34. ?controller area network (can)? (ds60001154) ? section 35. ?ethernet controller? (ds60001155) note 1: to access the documents listed below, browse to the documentation section of the pic32mx795f512l product page on the microchip web site ( www.microchip.com ) or select a family reference manual section from the following list. in addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections.
pic32mx5xx/6xx/7xx ds60001156h-page 32 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 33 pic32mx5xx/6xx/7xx 1.0 device overview this document contains devic e-specific information for pic32mx5xx/6xx/7xx devices. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the pic32mx5xx/6xx/ 7xx family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. figure 1-1: block diagram (1,2) note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: some features are not available on all devices. 2: bor functionality is provided when t he on-board voltage regulator is enabled. uart1-6 comparators porta portd porte portf portg portb cn1-22 jtag priority dmac icd mips32 ? m4k ? is ds ejtag int bus matrix prefetch data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 32 peripheral bus clocked by pbclk program flash memory controller 32 module 32 32 interrupt controller bscan portc pmp i2c1-5 spi1-4 ic1-5 pwm oc1-5 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap osc/s osc oscillators pll dividers sysclk pbclk peripheral bus clocked by sysclk usb pll-usb usbclk 32 rtcc 10-bit adc timer1-5 32 32 can1, can2 ethernet 32 32 cpu core
pic32mx5xx/6xx/7xx ds60001156h-page 34 ? 2009-2013 microchip technology inc. table 1-1: pinout i/o descriptions pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla an0 16 25 k2 b14 i analog analog input channels an1 15 24 k1 a15 i analog an2 14 23 j2 b13 i analog an3 13 22 j1 a13 i analog an4 12 21 h2 b11 i analog an5 11 20 h1 a12 i analog an6 17 26 l1 a20 i analog an7 18 27 j3 b16 i analog an8 21 32 k4 a23 i analog an9 22 33 l4 b19 i analog an10 23 34 l5 a24 i analog an11 24 35 j5 b20 i analog an12 27 41 j7 b23 i analog an13 28 42 l7 a28 i analog an14 29 43 k7 b24 i analog an15 30 44 l8 a29 i analog clki 39 63 f9 b34 i st/ cmos external clock sour ce input. always associated with osc1 pin function. clko 40 64 f11 a42 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 39 63 f9 b34 i st/ cmos oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. osc2 40 64 f11 a42 i/o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci 47 73 c10 a47 i st/ cmos 32.768 khz low-power oscillator crystal input; cmos otherwise sosco 48 74 b11 b40 o ? 32.768 khz low-power oscillator crystal output legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 35 pic32mx5xx/6xx/7xx cn0 48 74 b11 b40 i st change notification inputs. can be software programmed for internal weak pull-ups on all inputs. cn1 47 73 c10 a47 i st cn2 16 25 k2 b14 i st cn3 15 24 k1 a15 i st cn4 14 23 j2 b13 i st cn5 13 22 j1 a13 i st cn6 12 21 h2 b11 i st cn7 11 20 h1 a12 i st cn8 4 10 e3 a7 i st cn9 5 11 f4 b6 i st cn10 6 12 f2 a8 i st cn11 8 14 f3 a9 i st cn12 30 44 l8 a29 i st cn13 52 81 c8 b44 i st cn14 53 82 b8 a55 i st cn15 54 83 d7 b45 i st cn16 55 84 c7 a56 i st cn17 31 49 l10 b27 i st cn18 32 50 l11 a32 i st cn19 ? 80 d8 a54 i st cn20 ? 47 l9 b26 i st cn21 ? 48 k9 a31 i st ic1 42 68 e9 b37 i st capture inputs 1-5 ic2 43 69 e10 a45 i st ic3 44 70 d11 b38 i st ic4 45 71 c11 a46 i st ic5 52 79 a9 a60 i st ocfa 17 26 l1 a20 i st output compare fault a input oc1 46 72 d9 b39 o ? output compare output 1 oc2 49 76 a11 a52 o ? output compare output 2 oc3 50 77 a10 b42 o ? output compare output 3 oc4 51 78 b9 a53 o ? output compare output 4 oc5 52 81 c8 b44 o ? output compare output 5 ocfb 30 44 l8 a29 i st output compare fault b input int0 46 72 d9 b39 i st external interrupt 0 int1 42 18 g1 a11 i st external interrupt 1 int2 43 19 g2 b10 i st external interrupt 2 int3 44 66 e11 b36 i st external interrupt 3 int4 45 67 e8 a44 i st external interrupt 4 table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 36 ? 2009-2013 microchip technology inc. ra0 ? 17 g3 b9 i/o st porta is a bidirectional i/o port ra1 ? 38 j6 a26 i/o st ra2 ? 58 h11 a39 i/o st ra3 ? 59 g10 b32 i/o st ra4 ? 60 g11 a40 i/o st ra5 ? 61 g9 b33 i/o st ra6 ? 91 c5 b51 i/o st ra7 ? 92 b5 a62 i/o st ra9 ? 28 l2 a21 i/o st ra10 ? 29 k3 b17 i/o st ra14 ? 66 e11 b36 i/o st ra15 ? 67 e8 a44 i/o st rb0 16 25 k2 b14 i/o st portb is a bidirectional i/o port rb1 15 24 k1 a15 i/o st rb2 14 23 j2 b13 i/o st rb3 13 22 j1 a13 i/o st rb4 12 21 h2 b11 i/o st rb5 11 20 h1 a12 i/o st rb6 17 26 l1 a20 i/o st rb7 18 27 j3 b16 i/o st rb8 21 32 k4 a23 i/o st rb9 22 33 l4 b19 i/o st rb10 23 34 l5 a24 i/o st rb11 24 35 j5 b20 i/o st rb12 27 41 j7 b23 i/o st rb13 28 42 l7 a28 i/o st rb14 29 43 k7 b24 i/o st rb15 30 44 l8 a29 i/o st rc1 ? 6 d1 a5 i/o st portc is a bidirectional i/o port rc2 ? 7 e4 b4 i/o st rc3 ? 8 e2 a6 i/o st rc4 ? 9 e1 b5 i/o st rc12 39 63 f9 b34 i/o st rc13 47 73 c10 a47 i/o st rc14 48 74 b11 b40 i/o st rc15 40 64 f11 a42 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 37 pic32mx5xx/6xx/7xx rd0 46 72 d9 b39 i/o st portd is a bidirectional i/o port rd1 49 76 a11 a52 i/o st rd2 50 77 a10 b42 i/o st rd3 51 78 b9 a53 i/o st rd4 52 81 c8 b44 i/o st rd5 53 82 b8 a55 i/o st rd6 54 83 d7 b45 i/o st rd7 55 84 c7 a56 i/o st rd8 42 68 e9 b37 i/o st rd9 43 69 e10 a45 i/o st rd10 44 70 d11 b38 i/o st rd11 45 71 c11 a46 i/o st rd12 ? 79 a9 b43 i/o st rd13 ? 80 d8 a54 i/o st rd14 ? 47 l9 b26 i/o st rd15 ? 48 k9 a31 i/o st re0 60 93 a4 b52 i/o st porte is a bidirectional i/o port re1 61 94 b4 a64 i/o st re2 62 98 b3 a66 i/o st re3 63 99 a2 b56 i/o st re4 64 100 a1 a67 i/o st re5 1 3 d3 b2 i/o st re6 2 4 c1 a4 i/o st re7 3 5 d2 b3 i/o st re8 ? 18 g1 a11 i/o st re9 ? 19 g2 b10 i/o st rf0 58 87 b6 b49 i/o st portf is a bidirectional i/o port rf1 59 88 a6 a60 i/o st rf2 ? 52 k11 a36 i/o st rf3 33 51 k10 a35 i/o st rf4 31 49 l10 b27 i/o st rf5 32 50 l11 a32 i/o st rf8 ? 53 j10 b29 i/o st rf12 ? 40 k6 a27 i/o st rf13 ? 39 l6 b22 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 38 ? 2009-2013 microchip technology inc. rg0 ? 90 a5 a61 i/o st portg is a bidirectional i/o port rg1 ? 89 e6 b50 i/o st rg6 4 10 e3 a7 i/o st rg7 5 11 f4 b6 i/o st rg8 6 12 f2 a8 i/o st rg9 8 14 f3 a9 i/o st rg12 ? 96 c3 a65 i/o st rg13 ? 97 a3 b55 i/o st rg14 ? 95 c4 b54 i/o st rg15 ? 1 b2 a2 i/o st rg2 37 57 h10 b31 i st portg input pins rg3 36 56 j11 a38 i st t1ck 48 74 b11 b40 i st timer1 external clock input t2ck ? 6 d1 a5 i st timer2 external clock input t3ck ? 7 e4 b4 i st timer3 external clock input t4ck ? 8 e2 a6 i st timer4 external clock input t5ck ? 9 e1 b5 i st timer5 external clock input u1cts 43 47 l9 b26 i st uart1 clear to send u1rts 49 48 k9 a31 o ? uart1 ready to send u1rx 50 52 k11 a36 i st uart1 receive u1tx 51 53 j10 b29 o ? uart1 transmit u3cts 814f3 a9 i st uart3 clear to send u3rts 410e3 a7 o ? uart3 ready to send u3rx 511f4b6 i st uart3 receive u3tx 612f2a8 o ? uart3 transmit u2cts 21 40 k6 a27 i st uart2 clear to send u2rts 29 39 l6 b22 o ? uart2 ready to send u2rx 31 49 l10 b27 i st uart2 receive u2tx 32 50 l11 a32 o ? uart2 transmit u4rx 43 47 l9 b26 i st uart4 receive u4tx 49 48 k9 a31 o ? uart4 transmit u6rx 814f3a9 i st uart6 receive u6tx 410e3a7 o ? uart6 transmit u5rx 21 40 k6 a27 i st uart5 receive u5tx 29 39 l6 b22 o ? uart5 transmit sck1 ? 70 d11 b38 i/o st synchronous serial clock input/output for spi1 sdi1 ? 9 e1 b5 i st spi1 data in table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 39 pic32mx5xx/6xx/7xx sdo1 ? 72 d9 b39 o ? spi1 data out ss1 ?69e10 a45 i/o st spi1 slave synchronization or frame pulse i/o sck3 49 48 k9 a31 i/o st synchronous serial clock input/output for spi3 sdi3 50 52 k11 a36 i st spi3 data in sdo3 51 53 j10 b29 o ? spi3 data out ss3 43 47 l9 b26 i/o st spi3 slave synchronization or frame pulse i/o sck2 4 10 e3 a7 i/o st synchronous serial clock input/output for spi2 sdi2 5 11 f4 b6 i st spi2 data in sdo2 6 12 f2 a8 o ? spi2 data out ss2 814f3 a9 i/o st spi2 slave synchronization or frame pulse i/o sck4 29 39 l6 b22 i/o st synchronous serial clock input/output for spi4 sdi4 31 49 l10 b27 i st spi4 data in sdo4 32 50 l11 a32 o ? spi4 data out ss4 21 40 k6 a27 i/o st spi4 slave synchronization or frame pulse i/o scl1 44 66 e11 b36 i/o st synchronous serial clock input/output for i2c1 sda1 43 67 e8 a44 i/o st synchronous serial data input/output for i2c1 scl3 51 53 j10 b29 i/o st synchronous serial clock input/output for i2c3 sda3 50 52 k11 a36 i/o st synchronous serial data input/output for i2c3 scl2 ? 58 h11 a39 i/o st synchronous serial clock input/output for i2c2 sda2 ? 59 g10 b32 i/o st synchronous serial data input/output for i2c2 scl4 6 12 f2 a8 i/o st synchronous serial clock input/output for i2c4 sda4 5 11 f4 b6 i/o st synchronous serial data input/output for i2c4 scl5 32 50 l11 a32 i/o st synchronous serial clock input/output for i2c5 sda5 31 49 l10 b27 i/o st synchronous serial data input/output for i2c5 table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 40 ? 2009-2013 microchip technology inc. tms 23 17 g3 b9 i st jtag test mode select pin tck 27 38 j6 a26 i st jtag test clock input pin tdi 28 60 g11 a40 i st jtag test data input pin tdo 24 61 g9 b33 o ? jtag test data output pin rtcc 42 68 e9 b37 o ? real-time clock alarm output cv ref -1528l2 a21 i analog comparator voltage reference (low) cv ref + 16 29 k3 b17 i analog comparator voltage reference (high) cv refout 23 34 l5 a24 o analog comparator voltage reference output c1in- 12 21 h2 b11 i analog comparator 1 negative input c1in+ 11 20 h1 a12 i analog comparator 1 positive input c1out 21 32 k4 a23 o ? comparator 1 output c2in- 14 23 j2 b13 i analog comparator 2 negative input c2in+ 13 22 j1 a13 i analog comparator 2 positive input c2out 22 33 l4 b19 o ? comparator 2 output pma0 30 44 l8 a29 i/o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 k7 b24 i/o ttl/st parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 8 14 f3 a9 o ? parallel master port address (demultiplexed master modes) pma3 6 12 f2 a8 o ? pma4 5 11 f4 b6 o ? pma5 4 10 e3 a7 o ? pma6 16 29 k3 b17 o ? pma7 22 28 l2 a21 o ? pma8 32 50 l11 a32 o ? pma9 31 49 l10 b27 o ? pma10 28 42 l7 a28 o ? pma11 27 41 j7 b23 o ? pma12 24 35 j5 b20 o ? pma13 23 34 l5 a24 o ? pma14 45 71 c11 a46 o ? pma15 44 70 d11 b38 o ? pmcs1 45 71 c11 a46 o ? parallel master port chip select 1 strobe pmcs2 44 70 d11 b38 o ? parallel master port chip select 2 strobe table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 41 pic32mx5xx/6xx/7xx pmd0 60 93 a4 b52 i/o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd1 61 94 b4 a64 i/o ttl/st pmd2 62 98 b3 a66 i/o ttl/st pmd3 63 99 a2 b56 i/o ttl/st pmd4 64 100 a1 a67 i/o ttl/st pmd5 1 3 d3 b2 i/o ttl/st pmd6 2 4 c1 a4 i/o ttl/st pmd7 3 5 d2 b3 i/o ttl/st pmd8 ? 90 a5 a61 i/o ttl/st pmd9 ? 89 e6 b50 i/o ttl/st pmd10 ? 88 a6 a60 i/o ttl/st pmd11 ? 87 b6 b49 i/o ttl/st pmd12 ? 79 a9 b43 i/o ttl/st pmd13 ? 80 d8 a54 i/o ttl/st pmd14 ? 83 d7 b45 i/o ttl/st pmd15 ? 84 c7 a56 i/o ttl/st pmall 30 44 l8 a29 o ? parallel master port address latch enable low byte (multiplexed master modes) pmalh 29 43 k7 b24 o ? parallel master port address latch enable high byte (multiplexed master modes) pmrd 53 82 b8 a55 o ? parallel master port read strobe pmwr 52 81 c8 b44 o ? parallel ma ster port write strobe v bus 34 54 h8 a37 i analog usb bus power monitor v usb 3 v 3 35 55 h9 b30 p ? usb internal transceiver supply. if the usb module is not used, this pin must be connected to v dd . v buson 11 20 h1 a12 o ? usb host and otg bus power control output d+ 37 57 h10 b31 i/o analog usb d+ d- 36 56 j11 a38 i/o analog usb d- usbid 33 51 k10 a35 i st usb otg id detect c1rx 58 87 b6 b49 i st can1 bus receive pin c1tx 59 88 a6 a60 o ? can1 bus transmit pin ac1rx 32 40 k6 a27 i st alternate can1 bus receive pin ac1tx 31 39 l6 b22 o ? alternate can1 bus transmit pin c2rx 29 90 a5 a61 i st can2 bus receive pin c2tx 21 89 e6 b50 o ? can2 bus transmit pin ac2rx ? 8 e2 a6 1 st alternate can2 bus receive pin ac2tx ? 7 e4 b4 o ? alternate can2 bus transmit pin table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 42 ? 2009-2013 microchip technology inc. erxd0 61 41 j7 b23 i st ethernet receive data 0 (2) erxd1 60 42 l7 a28 i st ethernet receive data 1 (2) erxd2 59 43 k7 b24 i st ethernet receive data 2 (2) erxd3 58 44 l8 a29 i st ethernet receive data 3 (2) erxerr 64 35 j5 b20 i st ethernet receive error input (2) erxdv 62 12 f2 a8 i st ethernet receive data valid (2) ecrsdv 62 12 f2 a8 i st ethernet carrier sense data valid (2) erxclk 63 14 f3 a9 i st ethernet receive clock (2) erefclk 63 14 f3 a9 i st ethernet reference clock (2) etxd0 2 88 a6 a60 o ? ethernet transmit data 0 (2) etxd1 3 87 b6 b49 o ? ethernet transmit data 1 (2) etxd2 43 79 a9 b43 o ? ethernet transmit data 2 (2) etxd3 42 80 d8 a54 o ? ethernet transmit data 3 (2) etxerr 54 89 e6 b50 o ? ethernet transmit error (2) etxen 1 83 d7 b45 o ? ethernet transmit enable (2) etxclk 55 84 c7 a56 i st ethernet transmit clock (2) ecol 44 10 e3 a7 i st ethernet collision detect (2) ecrs 45 11 f4 b6 i st ethernet carrier sense (2) emdc 30 71 c11 a46 o ? ethernet management data clock (2) emdio 49 68 e9 b37 i/o ? ethernet management data (2) aerxd0 43 18 g1 a11 i st alternate ethernet receive data 0 (2) aerxd1 42 19 g2 b10 i st alternate ethernet receive data 1 (2) aerxd2 ? 28 l2 a21 i st alternate ethernet receive data 2 (2) aerxd3 ? 29 k3 b17 i st alternate ethernet receive data 3 (2) aerxerr 55 1 b2 a2 i st alternate et hernet receive error input (2) aerxdv ? 12 f2 a8 i st alternate ethernet receive data valid (2) aecrsdv 44 12 f2 a8 i st alternate ethernet carrier sense data valid (2) aerxclk ? 14 f3 a9 i st alternate ethernet receive clock (2) aerefclk 45 14 f3 a9 i st alternate ethernet reference clock (2) aetxd0 59 47 l9 b26 o ? alternate et hernet transmit data 0 (2) aetxd1 58 48 k9 a31 o ? alternate et hernet transmit data 1 (2) aetxd2 ? 44 l8 a29 o ? alternate ethernet transmit data 2 (2) aetxd3 ? 43 k7 b24 o ? alternate ethernet transmit data 3 (2) aetxerr ? 35 j5 b20 o ? alternate ethernet transmit error (2) aetxen 54 67 e8 a44 o ? alternate ethernet transmit enable (2) aetxclk ? 66 e11 b36 i st alternate ethernet transmit clock (2) aecol ? 42 l7 a28 i st alternate ethernet collision detect (2) aecrs ? 41 j7 b23 i st alternate ethernet carrier sense (2) table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 43 pic32mx5xx/6xx/7xx aemdc 30 71 c11 a46 o ? alternate ethernet management data clock (2) aemdio 49 68 e9 b37 i/o ? alternate ethernet management data (2) trclk ? 91 c5 b51 o ? trace clock trd0 ? 97 a3 b55 o ? trace data bits 0-3 trd1 ? 96 c3 a65 o ? trd2 ? 95 c4 b54 o ? trd3 ? 92 b5 a62 o ? pged1 16 25 k2 b14 i/o st data i/o pin for programming/ debugging communication channel 1 pgec1 15 24 k1 a15 i st clock input pin for programming/ debugging communication channel 1 pged2 18 27 j3 b16 i/o st data i/o pin for programming/ debugging communication channel 2 pgec2 17 26 l1 a20 i st clock input pin for programming/ debugging communication channel 2 mclr 713f1 b7 i/p st master clear (reset) input. this pin is an active-low rese t to the device. av dd 19 30 j4 a22 p p positive supply for analog modules. this pin must be connected at all times. av ss 20 31 l3 b18 p p ground reference for analog modules v dd 10, 26, 38, 57 2, 16, 37, 46, 62, 86 a7, c2, c9, e5, k8, f8, g5, h4, h6 a10, a14, a30, a41, a48, a59, b1, b21, b53 p? positive supply for peripheral logic and i/o pins v cap 56 85 b7 b48 p ? capacitor for internal voltage regulator v ss 9, 25, 41 15, 36, 45, 65, 75 a8, b10, d4, d5, e7, f5, f10, g6, g7, h3 a3, a25, a43, a63, b8, b12, b25, b41, b46 p? ground reference for logic and i/o pins. this pin must be connected at all times. v ref + 16 29 k3 b17 i analog analog voltage reference (high) input v ref - 15 28 l2 a21 i analog analog voltage reference (low) input table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin tfbga 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are only provided for reference. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 44 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 45 pic32mx5xx/6xx/7xx 2.0 guidelines for getting started with 32-bit mcus 2.1 basic connection requirements getting started with the pic32mx5xx/6xx/7xx family of 32-bit microcontrollers (mcus) requires attention to a minimal set of device pin connections before pro- ceeding with development. the following is a list of pin names, which must always be connected: ? all v dd and v ss pins (see 2.2 ?decoupling capacitors? ) ? all av dd and av ss pins even if the adc module is not used (see 2.2 ?decoupling capacitors? ) ?v cap pin (see 2.3 ?capacitor on internal voltage regulator (v cap )? ) ?mclr pin (see 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see 2.5 ?icsp pins? ) ? osc1 and osc2 pins when external oscillator source is used (see 2.8 ?external oscillator pins? ) the following pin may be required, as well: v ref +/ v ref - pins used when external voltage reference for adc module is implemented. 2.2 decoupling capacitors the use of decoupling capacitors on power supply pins, such as v dd , v ss , av dd and av ss is required. see figure 2-1 . consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a value of 0.1 f (100 nf), 10-20v is recommended. the capacitor should be a low equivalent series resistance (low-esr) capacitor and have resonance fre- quency in the range of 20 mhz and higher. it is further recommended to use ceramic capacitors. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended that the capacitors be placed on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb track inductance. figure 2-1: recommended minimum connection 2.2.1 bulk capacitors the use of a bulk capacitor is recommended to improve power supply stability. typical values range from 4.7 f to 47 f. this capacitor should be located as close to the device as possible. note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the av dd and av ss pins must be connected, regardless of the adc use and the adc voltage reference source. pic32mx v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c r v dd mclr 0.1 f ceramic v cap 10 ? r1 c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp c efc v usb 3 v 3 (1) note 1: if the usb module is used, this pin must be connected to v dd .
pic32mx5xx/6xx/7xx ds60001156h-page 46 ? 2009-2013 microchip technology inc. 2.3 capacitor on internal voltage regulator (v cap ) 2.3.1 internal regulator mode a low-esr (1 ohm) capaci tor is required on the v cap pin, which is used to stabilize the internal voltage regu- lator output. the v cap pin must not be connected to v dd , and must have a c efc capacitor, with at least a 6v rating, connected to ground. the type can be ceramic or tantalum. refer to section 31.0 ?electrical characteristics? for additional information on c efc specifications. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: ? device reset ? device programming and debugging pulling the mclr pin low generates a device reset. figure 2-2 illustrates a typical mclr circuit. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. th erefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as illustrated in figure 2-2 , it is recommended that the capa citor c, be isolated from the mclr pin during programming and debugging operations. place the components illustrated in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming s pecification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to mplab ? icd 3 or mplab ? real ice?. for more information on icd 3 and real ice connec- tion requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) (ds50001765) ? ?mplab ? icd 3 design advisory? (ds50001764) ? ?mplab ? real ice? in-circuit emulator user?s guide? ( ds50001616) ? ?using mplab ? real ice? emulator? (poster) (ds50001749) 2.6 jtag the tms, tdo, tdi and tck pins are used for testing and debugging according to the joint test action group (jtag) standard. it is recommended to keep the trace length between the jtag connector and the jtag pins on the device as short as possible. if the jtag connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the tms, tdo, tdi and tck pins are not recommended as they will interfere with the programmer/debugger communications to the device . if such discrete compo- nents are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc character- istics and timing requireme nts information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. note 1: r ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r1 ? 470 ? will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. 3: the capacitor can be sized to prevent uninten- tional resets from brief glitches or to extend the device reset period during the por. c (3) r1 (2) r (1) v dd mclr pic32 jp
? 2009-2013 microchip technology inc. ds60001156h-page 47 pic32mx5xx/6xx/7xx 2.7 trace the trace pins can be connected to a hardware-trace- enabled programmer to provide a compress real time instruction trace. when used for trace the trd3, trd2, trd1, trd0 and trclk pins should be dedicated for this use. th e trace hardware requires a22 ? series resistor between the trace pins and the trace connector. 2.8 external oscillator pins many mcus have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. refer to section 8.0 ?oscillator configuration? for details. the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator cir- cuit close to the respective oscillator pins, not exceed- ing one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscilla tor circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or po wer traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is illustrated in figure 2-3 . figure 2-3: suggested oscillator circuit placement 2.9 configuration of analog and digital pins during icsp operations if mplab icd 3 or real ice is selected as a debugger, it automatically initializes all of the analog- to-digital input pins (anx) as ?digital? pins by setting all bits in the ad1pcfg register. the bits in this register that correspond to the analog- to-digital pins that are initialized by mplab icd 3 or real ice, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain adc pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ad1pcfg register during initialization of the adc module. when mplab icd 3 or real ice is used as a pro- grammer, the user application firmware must correctly configure the ad1pcfg register. automatic initializa- tion of this register is only done during debugger oper- ation. failure to correctly configure the register(s) will result in all adc pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.10 unused i/os unused i/o pins should not be allowed to float as inputs. they can be configured as outputs and driven to a logic-low state. alternatively, inputs can be reserved by connecting the pin to v ss through a 1k to 10k resistor and configuring the pin as an input. main oscillator guard ring guard trace secondary oscillator
pic32mx5xx/6xx/7xx ds60001156h-page 48 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 49 pic32mx5xx/6xx/7xx 3.0 cpu the mips32 ? m4k ? processor core is the heart of the pic32mx5xx/6xx/7xx family processor. the cpu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 features ? 5-stage pipeline ? 32-bit address and data paths ? mips32 ? enhanced architecture (release 2) - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions ? mips16e ? code compression - 16-bit encoding of 32-bit instructions to improve code density - special pc-relative instructions for efficient loading of addresses and constants - save and restore macro instructions for setting up and tearing down stack frames within subroutines - improved support for handling 8-bit and 16-bit data types ? simple fixed mapping translation (fmt) mechanism ? simple dual bus interface - independent 32-bit address and data busses - transactions can be aborted to improve interrupt latency ? autonomous multiply/divide unit - maximum issue rate of one 32x16 multiply per clock - maximum issue rate of one 32x32 multiply every other clock - early-in iterative divide. minimum 11 and maximum 33 clock latency (dividend ( rs ) sign extension-dependent) ? power control - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ? ejtag debug and instruction trace - support for single stepping - virtual instruction and data address/value - breakpoints - pc tracing with trace compression figure 3-1: mips ? m4k ? processor core block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds60001113) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.micro- chip.com/pic32 ). resources for the mips32 ? m4k ? processor core are available at http://www.mips.com . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. cpu mdu execution core (rf/alu/shift) fmt tap ejtag bus interface power management system co-processor off-chip debug interface bus matrix dual bus interface
pic32mx5xx/6xx/7xx ds60001156h-page 50 ? 2009-2013 microchip technology inc. 3.2 architecture overview the mips ? m4k ? processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. the following blocks are in cluded with the core: ? execution unit ? multiply/divide unit (mdu) ? system control coprocessor (cp0) ? fixed mapping translation (fmt) ? dual internal bus interfaces ? power management ? mips16e ? support ? enhanced jtag (ejtag) controller 3.2.1 execution unit the mips ? m4k ? processor core execution unit imple- ments a load/store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autono- mous multiply/divide unit. the core contains thirty-two 32-bit general purpose registers (gprs) used for integer operations and address calculation. one addi- tional register file shadow set (containing thirty-two reg- isters) is added to minimize context switching overhead during interrupt/exception proc essing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: ? 32-bit adder used for calculating the data address ? address unit for calculating the next instruction address ? logic for branch determination and branch target address calculation ? load aligner ? bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results ? leading zero/one detect unit for implementing the clz and clo instructions ? arithmetic logic unit (alu) for performing bit-wise logical operations ? shifter and store aligner 3.2.2 multiply/divide unit (mdu) mips ? m4k ? processor core includes a multiply/divide unit (mdu) that contains a separate pipeline for multi- ply and divide operations. this pipeline operates in par- allel with the integer unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows mdu opera- tions to be partially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x16 booth recoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the pic32 core only checks t he value of the latter ( rt) operand to determine how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass through the multiplier once. a 32x32 operation passes through the multiplier twice. the mdu supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. the multiply operand size is automatically determined by logic built into the mdu. divide operations are implemented with a simple 1 bit per clock iterative algorith m. an early-in detection checks the sign extension of the dividend ( rs ) operand. if rs is 8 bits wide, 23 iterations are skipped. for a 16 bit wide rs , 15 iterations are skipped and for a 24 bit wide rs , 7 iterations are skipped. any attempt to issue a subsequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation is completed. table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num- ber of cycles until a result is available) for the pic32 core multiply and divide instructions. the approximate latency and repeat rates are listed in terms of pipeline clocks. table 3-1: mips ? m4k ? core high-performance integer multiply/divide unit latencies and repeat rates opcode operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu 16 bits 1 1 32 bits 2 2 mul 16 bits 2 1 32 bits 3 2 div/divu 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32
? 2009-2013 microchip technology inc. ds60001156h-page 51 pic32mx5xx/6xx/7xx the mips ? architecture defines that the result of a multiply or divide operation be placed in the hi and lo registers. using the move-from-hi ( mfhi ) and move- from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 ? architecture also defines a multiply instruc- tion, mul , which places the least significant results in the primary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction required when using the lo register , and by supporting multiple destination registers, the thro ughput of multiply-inten- sive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtra cts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. 3.2.3 system control coprocessor (cp0) in the mips ? architecture, cp0 is responsible for the virtual-to-physical address translation, the exception control system, the processor?s diagnostics capability, the operating modes (kernel, user and debug) and whether interrupts are enabled or disabled. configura- tion information, such as presence of options like mips16e ? , is also available by accessing the cp0 registers, listed in ta b l e 3 - 2 . table 3-2: coprocessor 0 registers register number register name function 0-6 reserved reserved. 7 hwrena enables access via the rdhwr instruction to select ed hardware registers. 8 badvaddr (1) reports the address for the most recent address-related exception. 9 count (1) processor cycle count. 10 reserved reserved. 11 compare (1) timer interrupt control. 12 status (1) processor status and control. 12 intctl (1) interrupt system status and control. 12 srsctl (1) shadow register set status and control. 12 srsmap (1) provides mapping from vectored interrupt to a shadow set. 13 cause (1) cause of last general exception. 14 epc (1) program counter at last exception. 15 prid processor identification and revision. 15 ebase exception vector base register. 16 config configuration register. 16 config1 configuration register 1. 16 config2 configuration register 2. 16 config3 configuration register 3. 17-22 reserved reserved. 23 debug (2) debug control and exception status. 24 depc (2) program counter at last debug exception. 25-29 reserved reserved. 30 errorepc (1) program counter at last error. 31 desave (2) debug handler scratchpad register. note 1: registers used in exception processing. 2: registers used during debug.
pic32mx5xx/6xx/7xx ds60001156h-page 52 ? 2009-2013 microchip technology inc. coprocessor 0 also contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. table 3-3 lists the exception types in order of priority. table 3-3: pic32mx5xx/6xx/7xx family core exception types exception description reset assertion mclr or a power-on reset (por). dss ejtag debug single step. dint ejtag debug interrupt. caused by the assertion of the external ej_dint input or by setting the ejtagbrk bit in the ecr register. nmi assertion of nmi signal. interrupt assertion of unmasked hardware or software interrupt signal. dib ejtag debug hardware instruction break matched. adel fetch address alignment error. fetch reference to protected address. ibe instruction fetch bus error. dbp ejtag breakpoint (execution of sdbbp instruction). sys execution of syscall instruction. bp execution of break instruction. ri execution of a reserved instruction. cpu execution of a coprocessor instruction for a coprocessor that is not enabled. ceu execution of a corextend instruction when corextend is not enabled. ov execution of an arithmetic instruction that overflowed. tr execution of a trap (when trap condition is true). ddbl/ddbs ejtag data address break (address only) or ejtag data value break on store (address + value). adel load address alignment error. load reference to protected address. ades store address alignment error. store to protected address. dbe load or store bus error. ddbl ejtag data hardware breakpoint matched in load data compare.
? 2009-2013 microchip technology inc. ds60001156h-page 53 pic32mx5xx/6xx/7xx 3.3 power management the mips ? m4k ? processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 instruction-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 27.0 ?power-saving features? . 3.3.2 local clock gating the majority of the power consumed by the pic32mx- 5xx/6xx/7xx family core is in the clock tree and clock- ing registers. the pic32 family uses extensive use of local gated clocks to reduce this dynamic power con- sumption. 3.4 ejtag debug support the mips ? m4k ? processor core provides for an enhanced jtag (ejtag) interface for use in the software debug of application and kernel code. in addition to standard user mode and kernel modes of operation, the mips ? m4k ? core provides a debug mode that is entered after a debug exception (derived from a hardware breakpoint , single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. during this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for transferring test data in and out of the mips ? m4k ? processor core. in addition to the standard jtag instructions, special instruct ions defined in the ejtag specification define which registers are selected and how they are used.
pic32mx5xx/6xx/7xx ds60001156h-page 54 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 55 pic32mx5xx/6xx/7xx 4.0 memory organization pic32mx5xx/6xx/7xx microcontrollers provide 4 gb of unified virtual memory address space. all memory regions, including program, data memory, sfrs and configuration registers, reside in this address space at their respective unique addresses. the program and data memories can be optionally partitioned into user and kernel memories. in addition, the data memory can be made executable, allowing pic32mx5xx/6xx/7xx devices to execute from data memory. key features include: ? 32-bit native data width ? separate user (kuseg) and kernel (kseg0/ kseg1) mode address space ? flexible program flash memory partitioning ? flexible data ram partitioning for data and program space ? separate boot flash memory for protected code ? robust bus exception handling to intercept runaway code ? simple memory mapping with fixed mapping translation (fmt) unit ? cacheable (kseg0) and non-cacheable (kseg1) address regions 4.1 memory layout pic32mx5xx/6xx/7xx microcontrollers implement two address schemes: virtual and physical. all hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. virtual addresses are exclusively used by the cpu to fetch and execute instructions as well as access peripheral s. physical addresses are used by bus master peripherals, such as dma and the flash controller, that access memory independently of the cpu. the memory maps for the pic32mx5xx/6xx/7xx devices are illustrated in figure 4-1 through figure 4-6 . 4.1.1 peripheral registers locations table 4-1 through ta b l e 4 - 4 4 contain the peripheral address maps for the pic32mx5xx/6xx/7xx devices. note: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. for detailed information, refer to section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ).
pic32mx5xx/6xx/7xx ds60001156h-page 56 ? 2009-2013 microchip technology inc. figure 4-1: memory map on reset fo r pic32mx564f064h, pic32mx564f064l, pic32mx664f064h and pic32mx664f064l devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool doc umentation for information). kseg1 kseg0
? 2009-2013 microchip technology inc. ds60001156h-page 57 pic32mx5xx/6xx/7xx figure 4-2: memory map on reset for pic32mx534f064h an d pic32mx534f064l devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0004000 0xa0003fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80004000 0x80003fff ram (2) 0x1d000000 reserved 0x80000000 0x00004000 reserved ram (2) 0x00003fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool doc umentation for information). kseg1 kseg0
pic32mx5xx/6xx/7xx ds60001156h-page 58 ? 2009-2013 microchip technology inc. figure 4-3: memory map on reset fo r pic32mx564f128h, pic32mx564f128l, pic32mx664f128h, pi c32mx664f128l, pi c32mx764f128h and PIC32MX764F128L devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd020000 0xbd01ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d020000 0x1f800000 0x9d01ffff program flash (2) reserved 0x9d000000 0x1d020000 reserved program flash (2) 0x1d01ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool doc umentation for information). kseg1 kseg0
? 2009-2013 microchip technology inc. ds60001156h-page 59 pic32mx5xx/6xx/7xx figure 4-4: memory map on reset fo r pic32mx575f256h, pic32mx575f256l, pic32mx675f256h, pi c32mx675f256l, pic32mx775f256h and pic32mx775f256l devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd040000 0xbd03ffff program flash (2) 0xbd000000 reserved 0xa0010000 0xa000ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d040000 0x1f800000 0x9d03ffff program flash (2) reserved 0x9d000000 0x1d040000 reserved program flash (2) 0x1d03ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00010000 reserved ram (2) 0x0000ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool doc umentation for information). kseg1 kseg0
pic32mx5xx/6xx/7xx ds60001156h-page 60 ? 2009-2013 microchip technology inc. figure 4-5: memory map on reset fo r pic32mx575f512h, pic32mx575f512l, pic32mx675f512h, pi c32mx675f512l, pi c32mx775f512h and pic32mx775f512l devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd080000 0xbd07ffff program flash (2) 0xbd000000 reserved 0xa0010000 0xa000ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d080000 0x1f800000 0x9d07ffff program flash (2) reserved 0x9d000000 0x1d080000 reserved program flash (2) 0x1d07ffff 0x80010000 0x8000ffff ram (2) 0x1d000000 reserved 0x80000000 0x00010000 reserved ram (2) 0x0000ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by init ialization code provided by end user development tools (refer to the specific devel opment tool documentation for information). kseg1 kseg0
? 2009-2013 microchip technology inc. ds60001156h-page 61 pic32mx5xx/6xx/7xx figure 4-6: memory map on reset fo r pic32mx695f512h, pic32mx695f512l, pic32mx795f512h and pic32mx795f512l devices virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd080000 0xbd07ffff program flash (2) 0xbd000000 reserved 0xa0020000 0xa001ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d080000 0x1f800000 0x9d07ffff program flash (2) reserved 0x9d000000 0x1d080000 reserved program flash (2) 0x1d07ffff 0x80020000 0x8001ffff ram (2) 0x1d000000 reserved 0x80000000 0x00020000 reserved ram (2) 0x0001ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115)) and can be changed by init ialization code provided by end user development tools (refer to the specific devel opment tool documentation for information). kseg1 kseg0
pic32mx5xx/6xx/7xx ds60001156h-page 62 ? 2009-2013 microchip technology inc. table 4-1: bus matrix register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 bmxcon (1) 31:16 ? ? ? ? ? bmxchedma ? ? ? ? ? bmxerrixi bmxerricd bmxerrdma bmxerrds bmxerris 001f 15:0 ? ? ? ? ? ? ? ? ?bmxwsdrm ? ? ? bmxarb<2:0> 0041 2010 bmxdkpba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdkpba<15:0> 0000 2020 bmxdudba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdudba<15:0> 0000 2030 bmxdupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdupba<15:0> 0000 2040 bmxdrmsz 31:16 bmxdrmsz<31:0> xxxx 15:0 xxxx 2050 bmxpupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? bmxpupba<19:16> 0000 15:0 bmxpupba<15:0> 0000 2060 bmxpfmsz 31:16 bmxpfmsz<31:0> xxxx 15:0 xxxx 2070 bmxbootsz 31:16 bmxbootsz<31:0> 0000 15:0 3000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 63 pic32mx5xx/6xx/7xx table 4-2: interrupt register map for pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h and pic32mx575f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/ 8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2 if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ? ? can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2 ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ? ? can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have correspond ing clr, set and inv registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564/664/764 devices. 3: this register does not have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 64 ? 2009-2013 microchip technology inc. 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ? ? ? ? ? 0000 table 4-2: interrupt register map for pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h and pic32mx575f512h devi ces (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/ 8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have correspond ing clr, set and inv registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564/664/764 devices. 3: this register does not have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 65 pic32mx5xx/6xx/7xx table 4-3: interrupt register map for pic32mx664f064h, pic32mx664f128h, pic32mx675f256h, pic32mx675f512h and pic32mx695f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif ? ? usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie ? ? usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does not have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 66 ? 2009-2013 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-3: interrupt register map for pic32mx664f064h, pic32mx664f128h, pic32mx675f256h, pic32mx675f512h and pic32mx695f512h devi ces (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does not have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 67 pic32mx5xx/6xx/7xx table 4-4: interrupt register map for pic32mx 764f128h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif can2if (2) can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie can2ie (2) can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128h device. 3: this register does not have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 68 ? 2009-2013 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? can2ip<2:0> (2) can2is<1:0> (2) ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-4: interrupt register map for pic32mx 764f128h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devi ces (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128h device. 3: this register does not have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 69 pic32mx5xx/6xx/7xx table 4-5: interrupt register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l pic32mx575f512l and pic32mx575f256l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ? ? can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ? ? can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564 devices. 3: this register does not have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 70 ? 2009-2013 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ? ? ? ? ? 0000 table 4-5: interrupt register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l pic32mx575f512l and pic32mx575f256l devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564 devices. 3: this register does not have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 71 pic32mx5xx/6xx/7xx table 4-6: interrupt register map fo r pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ? tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif ? ? usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie ? ? usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does note have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 72 ? 2009-2013 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-6: interrupt register map fo r pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does note have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 73 pic32mx5xx/6xx/7xx table 4-7: interrupt register map for pic32mx 764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif can2if (2) can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie can2ie (2) can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on PIC32MX764F128L device. 3: this register does not have associated clr, set, and inv registers.
pic32mx5xx/6xx/7xx ds60001156h-page 74 ? 2009-2013 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? can2ip<2:0> (2) can2is<1:0> (2) ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-7: interrupt register map for pic32mx 764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l d evices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on PIC32MX764F128L device. 3: this register does not have associated clr, set, and inv registers.
? 2009-2013 microchip technology inc. ds60001156h-page 75 pic32mx5xx/6xx/7xx table 4-8: timer1-timer5 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 t1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl twdis twip ? ? ?tgate ? tckps<1:0> ? tsync tcs ? 0000 0610 tmr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr1<15:0> 0000 0620 pr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr1<15:0> ffff 0800 t2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs (2) ? 0000 0810 tmr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr2<15:0> 0000 0820 pr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr2<15:0> ffff 0a00 t3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs (2) ? 0000 0a10 tmr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr3<15:0> 0000 0a20 pr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr3<15:0> ffff 0c00 t4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs (2) ? 0000 0c10 tmr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr4<15:0> 0000 0c20 pr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr4<15:0> ffff 0e00 t5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs (2) ? 0000 0e10 tmr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr5<15:0> 0000 0e20 pr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr5<15:0> ffff legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on 64-pin devices.
pic32mx5xx/6xx/7xx ds60001156h-page 76 ? 2009-2013 microchip technology inc. table 4-9: input capture 1-input capture 5 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ic1con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2010 ic1buf 31:16 ic1buf<31:0> xxxx 15:0 xxxx 2200 ic2con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2210 ic2buf 31:16 ic2buf<31:0> xxxx 15:0 xxxx 2400 ic3con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2410 ic3buf 31:16 ic3buf<31:0> xxxx 15:0 xxxx 2600 ic4con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2610 ic4buf 31:16 ic4buf<31:0> xxxx 15:0 xxxx 2800 ic5con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2810 ic5buf 31:16 ic5buf<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 77 pic32mx5xx/6xx/7xx table 4-10: output compare 1-output compare 5 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 oc1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3010 oc1r 31:16 oc1r<31:0> xxxx 15:0 xxxx 3020 oc1rs 31:16 oc1rs<31:0> xxxx 15:0 xxxx 3200 oc2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3210 oc2r 31:16 oc2r<31:0> xxxx 15:0 xxxx 3220 oc2rs 31:16 oc2rs<31:0> xxxx 15:0 xxxx 3400 oc3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3410 oc3r 31:16 oc3r<31:0> xxxx 15:0 xxxx 3420 oc3rs 31:16 15:0 oc3rs<31:0> xxxx xxxx 3600 oc4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3610 oc4r 31:16 oc4r<31:0> xxxx 15:0 xxxx 3620 oc4rs 31:16 15:0 oc4rs<31:0> xxxx xxxx 3800 oc5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3810 oc5r 31:16 oc5r<31:0> xxxx 15:0 xxxx 3820 oc5rs 31:16 oc5rs<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 78 ? 2009-2013 microchip technology inc. table 4-11: i2c1, i2c3, i2c4 and i2c5 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 i2c3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5010 i2c3stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5020 i2c3add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5030 i2c3msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5040 i2c3brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5050 i2c3trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5060 i2c3rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5100 i2c4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5110 i2c4stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5120 i2c4add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5130 i2c4msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5140 i2c4brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5150 i2c4trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5160 i2c4rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5200 i2c5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5210 i2c5stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 79 pic32mx5xx/6xx/7xx 5220 i2c5add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5230 i2c5msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5240 i2c5brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5250 i2c5trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5260 i2c5rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5300 i2c1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5310 i2c1stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5320 i2c1add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5330 i2c1msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5340 i2c1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5350 i2c1trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5360 i2c1rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 table 4-11: i2c1, i2c3, i2c4 and i2c5 register map (continued) virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 80 ? 2009-2013 microchip technology inc. table 4-12: i2c2 register map for pic32mx534f064l, pic32mx564f064l, pi c32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5400 i2c2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5410 i2c2stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5420 i2c2add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5430 i2c2msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5440 i2c2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5450 i2c2trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5460 i2c2rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 81 pic32mx5xx/6xx/7xx table 4-13: uart1 through uart6 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 u1mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6010 u1sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6020 u1txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6030 u1rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6040 u1brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6200 u4mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidliren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6210 u4sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6220 u4txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6230 u4rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6240 u4brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6400 u3mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6410 u3sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6420 u3txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6430 u3rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6440 u3brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6600 u6mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidliren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6610 u6sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6620 u6txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 82 ? 2009-2013 microchip technology inc. 6630 u6rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6640 u6brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6800 u2mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6810 u2sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6820 u2txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6830 u2rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6840 u2brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6a00 u5mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidliren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6a10 u5sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6a20 u5txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6a30 u5rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6a40 u5brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 table 4-13: uart1 through uart6 register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 83 pic32mx5xx/6xx/7xx table 4-14: spi2, spi3 and spi4 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 spi3con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5810 spi3stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5820 spi3buf 31:16 data<31:0> 0000 15:0 0000 5830 spi3brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? brg<8:0> 0000 5a00 spi2con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5a10 spi2stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5a20 spi2buf 31:16 data<31:0> 0000 15:0 0000 5a30 spi2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? brg<8:0> 0000 5c00 spi4con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5c10 spi4stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5c20 spi4buf 31:16 data<31:0> 0000 15:0 0000 5c30 spi4brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? brg<8:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 84 ? 2009-2013 microchip technology inc. table 4-15: spi1 register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5e00 spi1con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5e10 spi1stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ? spitbe ? spitbf spirbf 0008 5e20 spi1buf 31:16 data<31:0> 0000 15:0 0000 5e30 spi1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spi1buf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 85 pic32mx5xx/6xx/7xx table 4-16: adc register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ad1con1 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? form<2:0> ssrc<2:0> clrasam ? asam samp done 0000 9010 ad1con2 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 vcfg2 vcfg1 vcfg0 offcal ?cscna ? ?bufs ? smpi<3:0> bufm alts 0000 9020 ad1con3 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 adrc ? ? samc<4:0> adcs<7:0> 0000 9040 ad1chs (1) 31:16 ch0nb ? ? ? ch0sb<3:0> ch0na ? ? ? ch0sa<3:0> 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 9060 ad1pcfg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pcfg15 pcfg14 pcfg13 pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 9050 ad1cssl (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 9070 adc1buf0 31:16 adc result word 0 (adc1buf0<31:0>) 0000 15:0 0000 9080 adc1buf1 31:16 adc result word 1 (adc1buf1<31:0>) 0000 15:0 0000 9090 adc1buf2 31:16 adc result word 2 (adc1buf2<31:0>) 0000 15:0 0000 90a0 adc1buf3 31:16 adc result word 3 (adc1buf3<31:0>) 0000 15:0 0000 90b0 adc1buf4 31:16 adc result word 4 (adc1buf4<31:0>) 0000 15:0 0000 90c0 adc1buf5 31:16 adc result word 5 (adc1buf5<31:0>) 0000 15:0 0000 90d0 adc1buf6 31:16 adc result word 6 (adc1buf6<31:0>) 0000 15:0 0000 90e0 adc1buf7 31:16 adc result word 7 (adc1buf7<31:0>) 0000 15:0 0000 90f0 adc1buf8 31:16 adc result word 8 (adc1buf8<31:0>) 0000 15:0 0000 9100 adc1buf9 31:16 adc result word 9 (adc1buf9<31:0>) 0000 15:0 0000 9110 adc1bufa 31:16 adc result word a (adc1bufa<31:0>) 0000 15:0 0000 9120 adc1bufb 31:16 adc result word b (adc1bufb<31:0>) 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 86 ? 2009-2013 microchip technology inc. 9130 adc1bufc 31:16 adc result word c (adc1bufc<31:0>) 0000 15:0 0000 9140 adc1bufd 31:16 adc result word d (adc1bufd<31:0>) 0000 15:0 0000 9150 adc1bufe 31:16 adc result word e (adc1bufe<31:0>) 0000 15:0 0000 9160 adc1buff 31:16 adc result word f (adc1buff<31:0>) 0000 15:0 0000 table 4-16: adc register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 87 pic32mx5xx/6xx/7xx table 4-17: dma global register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 dmacon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? suspend dmabusy ? ? ? ? ? ? ? ? ? ? ? 0000 3010 dmastat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rdwr dmach<2:0> (2) 0000 3020 dmaaddr 31:16 dmaaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dmach<3> bit is not available on pic32mx534/564/664/764 devices. table 4-18: dma crc register map (1) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 dcrccon 31:16 ? ? byto<1:0> wbo ? ?bito ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? plen<4:0> crcen crcapp crctyp ? ? crcch<2:0> 0000 3040 dcrcdata 31:16 dcrcdata<31:0> 0000 15:0 0000 3050 dcrcxor 31:16 dcrcxor<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 88 ? 2009-2013 microchip technology inc. table 4-19: dma channels 0-7 register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 dch0con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3070 dch0econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3080 dch0int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3090 dch0ssa 31:16 chssa<31:0> 0000 15:0 0000 30a0 dch0dsa 31:16 chdsa<31:0> 0000 15:0 0000 30b0 dch0ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 30c0 dch0dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 30d0 dch0sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 30e0 dch0dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 30f0 dch0csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3100 dch0cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3110 dch0dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3120 dch1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3130 dch1econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3140 dch1int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3150 dch1ssa 31:16 chssa<31:0> 0000 15:0 0000 3160 dch1dsa 31:16 chdsa<31:0> 0000 15:0 0000 3170 dch1ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
? 2009-2013 microchip technology inc. ds60001156h-page 89 pic32mx5xx/6xx/7xx 3180 dch1dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3190 dch1sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 31a0 dch1dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 31b0 dch1csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 31c0 dch1cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 31d0 dch1dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 31e0 dch2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 31f0 dch2econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3200 dch2int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3210 dch2ssa 31:16 chssa<31:0> 0000 15:0 0000 3220 dch2dsa 31:16 chdsa<31:0> 0000 15:0 0000 3230 dch2ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3240 dch2dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3250 dch2sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3260 dch2dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3270 dch2csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3280 dch2cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 table 4-19: dma channels 0-7 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
pic32mx5xx/6xx/7xx ds60001156h-page 90 ? 2009-2013 microchip technology inc. 3290 dch2dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 32a0 dch3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 32b0 dch3econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 32c0 dch3int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 32d0 dch3ssa 31:16 chssa<31:0> 0000 15:0 0000 32e0 dch3dsa 31:16 chdsa<31:0> 0000 15:0 0000 32f0 dch3ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3300 dch3dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3310 dch3sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3320 dch3dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3330 dch3csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3340 dch3cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3350 dch3dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3360 dch4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3370 dch4econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3380 dch4int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3390 dch4ssa 31:16 chssa<31:0> 0000 15:0 0000 33a0 dch4dsa 31:16 chdsa<31:0> 0000 15:0 0000 table 4-19: dma channels 0-7 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
? 2009-2013 microchip technology inc. ds60001156h-page 91 pic32mx5xx/6xx/7xx 33b0 dch4ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz15:0> 0000 33c0 dch4dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 33d0 dch4sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 33e0 dch4dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 33f0 dch4csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3400 dch4cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3410 dch4dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3420 dch5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3430 dch5econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3440 dch5int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3450 dch5ssa 31:16 chssa<31:0> 0000 15:0 0000 3460 dch5dsa 31:16 chdsa<31:0> 0000 15:0 0000 3470 dch5ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3480 dch5dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3490 dch5sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 34a0 dch5dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 34b0 dch5csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 34c0 dch5cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 table 4-19: dma channels 0-7 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
pic32mx5xx/6xx/7xx ds60001156h-page 92 ? 2009-2013 microchip technology inc. 34d0 dch5dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 34e0 dch6con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 34f0 dch6econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3500 dch6int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3510 dch6ssa 31:16 chssa<31:0> 0000 15:0 0000 3520 dch6dsa 31:16 chdsa<31:0> 0000 15:0 0000 3530 dch6ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3540 dch6dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3550 dch6sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3560 dch6dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3570 dch6csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3580 dch6cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3590 dch6dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 35a0 dch7con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 35b0 dch7econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 35c0 dch7int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 35d0 dch7ssa 31:16 chssa<31:0> 0000 15:0 0000 35e0 dch7dsa 31:16 chdsa<31:0> 0000 15:0 0000 table 4-19: dma channels 0-7 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
? 2009-2013 microchip technology inc. ds60001156h-page 93 pic32mx5xx/6xx/7xx 35f0 dch7ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3600 dch7dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3610 dch7sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3620 dch7dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3630 dch7csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3640 dch7cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3650 dch7dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 table 4-19: dma channels 0-7 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are not available on pic32mx534/564/664/764 devices.
pic32mx5xx/6xx/7xx ds60001156h-page 94 ? 2009-2013 microchip technology inc. table 4-20: comparator register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a000 cm1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a010 cm2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a060 cmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ?sidl ? ? ? ? ? ? ? ? ? ? ? c2out c1out 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-21: comparator voltage reference register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 cvrcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ?vrefsel (2) bgsel<1:0> (2) ? cvroe cvrr cvrss cvr<3:0> 0100 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx575/675/695/775/795 devi ces. on these devices, reset value for cvrcon is ? 0000 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 95 pic32mx5xx/6xx/7xx table 4-22: flash controller register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f400 nvmcon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 wr wren wrerr lvderr lvdstat ? ? ? ? ? ? ? nvmop<3:0> 0000 f410 nvmkey 31:16 nvmkey<31:0> 0000 15:0 0000 f420 nvmaddr (1) 31:16 nvmaddr<31:0> 0000 15:0 0000 f430 nvmdata 31:16 nvmdata<31:0> 0000 15:0 0000 f440 nvmsrc addr 31:16 nvmsrcaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-23: system control register map virtual address (bf80_#) register name (1) bit range bits all resets (2) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f000 osccon 31:16 ? ? pllodiv<2:0> frcdiv<2:0> ? soscrdy ? pbdiv<1:0> pllmult<2:0> 0000 15:0 ?cosc<2:0> ? nosc<2:0> clklock ulock slock slpen cf ufrcen soscen oswen 0000 f010 osctun 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? tun<5:0> 0000 0000 wdtcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? swdtps<4:0> ? wdtclr 0000 f600 rcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cmr vregs extr swr ? wdto sleep idle bor por 0000 f610 rswrst 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?swrst 0000 f230 syskey 31:16 syskey<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset.
pic32mx5xx/6xx/7xx ds60001156h-page 96 ? 2009-2013 microchip technology inc. table 4-24: porta register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 trisa 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisa15 trisa14 ? ? ? trisa10 trisa9 ? trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 c6ff 6010 porta 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ra15 ra14 ? ? ?ra10ra9 ? ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 6020 lata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lata15 lata14 ? ? ? lata10 lata9 ? lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx 6030 odca 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odca15 odca14 ? ? ? odca10 odca9 ? odca7 odca6 odca5 odca4 odca3 odca2 odca1 odca0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-25: portb register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6040 trisb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff 6050 portb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 6060 latb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx 6070 odcb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcb15 odcb14 odcb13 odcb12 odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 odcb3 odcb2 odcb1 odcb0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 97 pic32mx5xx/6xx/7xx table 4-26: portc register map for pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx764f128h, pic32mx775f256h, pic32m x775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? ? ? ? ? ? f000 6090 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 60a0 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 60b0 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcc15 odcc14 odcc13 odcc12 ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-27: portc register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? f00f 6090 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? xxxx 60a0 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? xxxx 60b0 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcc15 odcc14 odcc13 odcc12 ? ? ? ? ? ? ? odcc4 odcc3 odcc2 odcc1 ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 98 ? 2009-2013 microchip technology inc. table 4-28: portd register map for pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60c0 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 0fff 60d0 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 60e0 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 60f0 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-29: portd register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60c0 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 ffff 60d0 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 60e0 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lat15 lat14 lat13 lat12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 60f0 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 99 pic32mx5xx/6xx/7xx table 4-30: porte register map for pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 00ff 6110 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6120 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6130 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? odce7 0dce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-31: porte register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 03ff 6110 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? re9 re8 re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6120 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ?late9late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6130 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odce9 odce8 odce7 0dce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 100 ? 2009-2013 microchip technology inc. table 4-32: portf register map for pic32mx534f064h, pic32mx564f064 h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? trisf5 trisf4 trisf3 ? trisf1 trisf0 003b 6150 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ?rf5rf4rf3 ?rf1rf0 xxxx 6160 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? latf5 latf4 latf3 ? latf1 latf0 xxxx 6170 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? odcf5 odcf4 odcf3 ? odcf1 odcf0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-33: portf register ma p pic32mx534f064l, pic32mx564f0 64l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx775f256l, PIC32MX764F128L, pic32mx775f512 l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? trisf13 trisf12 ? ? ?trisf8 ? ? trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 313f 6150 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? rf13 rf12 ? ? ?rf8 ? ? rf5 rf4 rf3 rf2 rf1 rf0 xxxx 6160 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? latf13 latf12 ? ? ? latf8 ? ? latf5 latf4 latf3 latf2 latf1 latf0 xxxx 6170 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? odcf13 odcf12 ? ? ? odcf8 ? ? odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 101 pic32mx5xx/6xx/7xx table 4-34: portg register map fo r pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx764f128h, pic32mx775f256h, pic32m x775f512h and pic32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 ? ? 03cc 6190 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? rg9 rg8 rg7 rg6 ? ?rg3rg2 ? ? xxxx 61a0 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? latg9 latg8 latg7 latg6 ? ?latg3latg2 ? ? xxxx 61b0 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odcg9 odcg8 odcg7 odcg6 ? ? odcg3 odcg2 ? ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-35: portg register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675 f512l, pic32mx695f512l, PIC32MX764F128L, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisg15 trisg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 f3cf 6190 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rg15 rg14 rg13 rg12 ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 xxxx 61a0 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 xxxx 61b0 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcg15 odcg14 odcg13 odcg12 ? ? odcg9 odcg8 odcg7 odcg6 ? ? odcg3 odcg2 odcg1 odcg0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 102 ? 2009-2013 microchip technology inc. table 4-36: change notice and pull-up register map for pic32mx534f064l, pic32mx5 64f064l, pic32m x564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx 764f128l, pic32mx775f256l, pic32mx7 75f512 and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61c0 cncon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 61d0 cnen 31:16 ? ? ? ? ? ? ? ? ? ? cnen21 cnen20 cnen19 cnen18 cnen17 cnen16 0000 15:0 cnen15 cnen14 cnen13 cnen12 cnen11 cnen10 cnen9 cnen8 cnen7 cnen6 cnen5 cnen4 cnen3 cnen2 cnen1 cnen0 0000 61e0 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? cnpue21 cnpue20 cnpue19 cnpue18 cnpue17 cnpue16 0000 15:0 cnpue15 cnpue14 cnpue13 cnpue12 cnpue11 cnpue10 cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-37: change notice and pull-up register map for pic32mx575f256h, pic32mx5 75f512h, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h , pic32mx775f512h and pi c32mx795f512h devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61c0 cncon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 61d0 cnen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? cnen18 cnen17 cnen16 0000 15:0 cnen15 cnen14 cnen13 cnen12 cnen11 cnen10 cnen9 cnen8 cnen7 cnen6 cnen5 cnen4 cnen3 cnen2 cnen1 cnen0 0000 61e0 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? cnpue18 cnpue17 cnpue16 0000 15:0 cnpue15 cnpue14 cnpue13 cnpue12 cnpue11 cnpue10 cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 103 pic32mx5xx/6xx/7xx table 4-38: parallel mast er port register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 pmcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl adrmux<1:0> pmpttl ptwren ptrden csf<1:0> alp cs2p cs1p ? wrsp rdsp 0000 7010 pmmode 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> waitb<1:0> waitm<3:0> waite<1:0> 0000 7020 pmaddr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cs2en/a15 cs1en/a14 addr<13:0> 0000 7030 pmdout 31:16 dataout<31:0> 0000 15:0 0000 7040 pmdin 31:16 datain<31:0> 0000 15:0 0000 7050 pmaen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pten<15:0> 0000 7060 pmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 008f legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-39: programming and diagnostics register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f200 ddpcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?jtagentroen ?tdoen 0008 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic32mx5xx/6xx/7xx ds60001156h-page 104 ? 2009-2013 microchip technology inc. table 4-40: prefetch register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 checon (1,2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? checoh 0000 15:0 ? ? ? ? ? ? dcsz<1:0> ? ? prefen<1:0> ? pfmws<2:0> 0007 4010 cheacc (1) 31:16 chewen ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? cheidx<3:0> 0000 4020 chetag (1) 31:16 ltagboot ? ? ? ? ? ? ? ltag<23:16> 00xx 15:0 ltag<15:4> lvalid llock ltype ? xxx2 4030 chemsk (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lmask<15:5> ? ? ? ? ? 0000 4040 chew0 31:16 chew0<31:0> xxxx 15:0 xxxx 4050 chew1 31:16 chew1<31:0> xxxx 15:0 xxxx 4060 chew2 31:16 chew2<31:0> xxxx 15:0 xxxx 4070 chew3 31:16 chew3<31:0> xxxx 15:0 xxxx 4080 chelru 31:16 ? ? ? ? ? ? ? chelru<24:16> 0000 15:0 chelru<15:0> 0000 4090 chehit 31:16 chehit<31:0> xxxx 15:0 xxxx 40a0 chemis 31:16 chemis<31:0> xxxx 15:0 xxxx 40c0 chepfabt 31:16 chepfabt<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset value is dependent on devcfgx configuration.
? 2009-2013 microchip technology inc. ds60001156h-page 105 pic32mx5xx/6xx/7xx table 4-41: rtcc register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 rtccon 31:16 ? ? ? ? ? ? cal<9:0> 0000 15:0 on ?sidl ? ? ? ? ? rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe 0000 0210 rtcalrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 alrmen chime piv alrmsync amask<3:0> arpt<7:0> 0000 0220 rtctime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0230 rtcdate 31:16 year10<3:0> year01<3:0> month10<3:0> month01<3:0> xxxx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx00 0240 alrmtime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0250 alrmdate 31:16 ? ? ? ? ? ? ? ? month10<3:0> month01<3:0> 00xx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx0x legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 106 ? 2009-2013 microchip technology inc. table 4-42: devcfg: device configuration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2ff0 devcfg3 31:16 fvbusonio fusbidio ? ? ? fcanio fethio fmiien ? ? ? ? ? fsrssel<2:0> xxxx 15:0 userid<15:0> xxxx 2ff4 devcfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? fpllodiv<2:0> xxxx 15:0 upllen ? ? ? ? upllidiv<2:0> ? fpllmul<2:0> ? fpllidiv<2:0> xxxx 2ff8 devcfg1 31:16 ? ? ? ? ? ? ? ?fwdten ? ? wdtps<4:0> xxxx 15:0 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> ieso ? fsoscen ? ?fnosc<2:0> xxxx 2ffc devcfg0 31:16 ? ? ?cp ? ? ?bwp ? ? ? ?pwp<7:4> xxxx 15:0 pwp<3:0> ? ? ? ? ? ? ? ? icesel ? debug<1:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-43: device and revision id summary virtual address (bf80_#) register name bit range bits all resets (1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f220 devid 31:16 ver<3:0> devid<27:16> xxxx 15:0 devid<15:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset values are dependent on the device variant. refer to ?pic32mx5xx/6xx/7xx family silicon errata and data sheet clarification? (ds80000480) for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 107 pic32mx5xx/6xx/7xx table 4-44: usb register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 u1otgir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 5050 u1otgie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 5060 u1otgstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 5070 u1otgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 5080 u1pwrc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?uactpnd (4) ? ? uslpgrd usbbusy ? ususpend usbpwr 0000 5200 u1ir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallif attachif resumeif idleif trnif sofif uerrif urstif 0000 detachif 0000 5210 u1ie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallie attachie resumeie idleie trnie sofie uerrie urstie 0000 detachie 0000 5220 u1eir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 eofef 0000 5230 u1eie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 eofee 0000 5240 u1stat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? endpt<3:0> (4) dir ppbi ? ? 0000 5250 u1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?jstate (4) se0 (4) pktdis usbrst hosten resume ppbrst usben 0000 tokbusy sofen 0000 5260 u1addr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspden devaddr<6:0> 0000 5270 u1bdtp1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrl<7:1> ? 0000 5280 u1frml (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? frml<7:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined.
pic32mx5xx/6xx/7xx ds60001156h-page 108 ? 2009-2013 microchip technology inc. 5290 u1frmh (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? frmh<2:0> 0000 52a0 u1tok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? pid<3:0> ep<3:0> 0000 52b0 u1sof 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cnt<7:0> 0000 52c0 u1bdtp2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrh<7:0> 0000 52d0 u1bdtp3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptru<7:0> 0000 52e0 u1cnfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? uteye uoemon ? usbsidl ? ? ? uasuspnd 0001 5300 u1ep0 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspd retrydis ? epcondis eprxen eptxen epstall ephshk 0000 5310 u1ep1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5320 u1ep2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5330 u1ep3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5340 u1ep4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5350 u1ep5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5360 u1ep6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5370 u1ep7 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5380 u1ep8 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5390 u1ep9 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53a0 u1ep10 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-44: usb register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined.
? 2009-2013 microchip technology inc. ds60001156h-page 109 pic32mx5xx/6xx/7xx 53b0 u1ep11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53c0 u1ep12 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53d0 u1ep13 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53e0 u1ep14 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53f0 u1ep15 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-44: usb register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined.
pic32mx5xx/6xx/7xx ds60001156h-page 110 ? 2009-2013 microchip technology inc. table 4-45: can1 register summary fo r pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx764f128h, pic32mx775f256h, pi c32mx775f512h, pic32mx795f512h, pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, PIC32MX764F128L, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 b000 c1con 31:16 ? ? ? ? abat reqop<2:0> opmod<2:0> cancap ? ? ? ? 0480 15:0 on ?sidle ? canbusy ? ? ? ? ? ? dncnt<4:0> 0000 b010 c1cfg 31:16 ? ? ? ? ? ? ? ? ? wakfil ? ? ? seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 b020 c1int 31:16 ivrie wakie cerrie serrie rbovie ? ? ? ? ? ? ? modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif ? ? ? ? ? ? ? modif ctmrif rbif tbif 0000 b030 c1vec 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? filhit<4:0> ? icode<6:0> 0040 b040 c1trec 31:16 ? ? ? ? ? ? ? ? ? ? txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 b050 c1fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fi foip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 b060 c1rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 b070 c1tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 b080 c1rxm0 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b090 c1rxm1 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0a0 c1rxm2 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0b0 c1rxm3 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0c0 c1fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 b0d0 c1fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 b0e0 c1fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 b0f0 c1fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 111 pic32mx5xx/6xx/7xx b100 c1fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0> 0000 b110 c1fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 b120 c1fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 b130 c1fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 b140 c1rxfn (n = 0-31) 31:16 sid<10:0> -? exid ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b340 c1fifoba 31:16 c1fifoba<31:0> 0000 15:0 0000 b350 c1fifoconn (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? fsize<4:0> 0000 15:0 ? freset uinc donly ? ? ? ? txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 b360 c1fifointn (n = 0-31) 31:16 ? ? ? ? ? txnfullie txhalfie txemptyie ? ? ? ? rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 ? ? ? ? ? txnfullif txhalfif txemptyif ? ? ? ? rxovflif rxfullif rxhalfif rxn emptyif 0000 b370 c1fifouan (n = 0-31) 31:16 c1fifoua<31:0> 0000 15:0 0000 b380 c1fifocin (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? c1fifoci<4:0> 0000 table 4-45: can1 register summary fo r pic32mx534f064h, pic32mx564f064h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx764f128h, pic32mx775f256h, pi c32mx775f512h, pic32mx795f512h, pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, PIC32MX764F128L, pic32mx775f256l, pic32mx775f512l and pic32mx795 f512l devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 112 ? 2009-2013 microchip technology inc. table 4-46: can2 register summary fo r pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 c000 c2con 31:16 ? ? ? ? abat reqop<2:0> opmod<2:0> cancap ? ? ? ? 0480 15:0 on ?sidle ? canbusy ? ? ? ? ? ? dncnt<4:0> 0000 c010 c2cfg 31:16 ? ? ? ? ? ? ? ? ? wakfil ? ? ? seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 c020 c2int 31:16 ivrie wakie cerrie serrie rbovie ? ? ? ? ? ? ? modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif ? ? ? ? ? ? ? modif ctmrif rbif tbif 0000 c030 c2vec 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? filhit<4:0> ? icode<6:0> 0040 c040 c2trec 31:16 ? ? ? ? ? ? ? ? ? ? txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 c050 c2fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fi foip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 c060 c2rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 c070 c2tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 c080 c2rxm0 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0a0 c2rxm1 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0b0 c2rxm2 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0b0 c2rxm3 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0c0 c2fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 c0d0 c2fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 c0e0 c2fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 c0f0 c2fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
? 2009-2013 microchip technology inc. ds60001156h-page 113 pic32mx5xx/6xx/7xx c100 c2fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0: 0000 c110 c2fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 c120 c2fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 c130 c2fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 c140 c2rxfn (n = 0-31) 31:16 sid<10:0> -? exid ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c340 c2fifoba 31:16 c2fifoba<31:0> 0000 15:0 0000 c350 c2fifoconn (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? fsize<4:0> 0000 15:0 ? freset uinc donly ? ? ? ? txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 c360 c2fifointn (n = 0-31) 31:16 ? ? ? ? ? txnfullie txhalfie txemptyie ? ? ? ? rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 ? ? ? ? ? txnfullif txhalfif txemptyif ? ? ? ? rxovflif rxfullif rxhalfif rxn emptyif 0000 c370 c2fifouan (n = 0-31) 31:16 c2fifoua<31:0> 0000 15:0 0000 c380 c2fifocin (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? c2fifoci<4:0> 0000 table 4-46: can2 register summary fo r pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx775f256l, pic32mx775f512l and pic32mx795 f512l devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 114 ? 2009-2013 microchip technology inc. table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, PIC32MX764F128L, pic32mx775f256l, pic32mx775f512 l and pic32mx795f512l devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ethcon1 31:16 ptv<15:0> 0000 15:0 on ?sidl ? ? ? txrts rxen autofc ? ?manfc ? ? ? bufcdec 0000 9010 ethcon2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? rxbufsz<6:0> ? ? ? ? 0000 9020 ethtxst 31:16 txstaddr<31:16> 0000 15:0 txstaddr<15:2> ? ? 0000 9030 ethrxst 31:16 rxstaddr<31:16> 0000 15:0 rxstaddr<15:2> ? ? 0000 9040 ethht0 31:16 ht<31:0> 0000 15:0 0000 9050 ethht1 31:16 ht<63:32> 0000 15:0 0000 9060 ethpmm0 31:16 pmm<31:0> 0000 15:0 0000 9070 ethpmm1 31:16 pmm<63:32> 0000 15:0 0000 9080 ethpmcs 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pmcs<15:0> 0000 9090 ethpmo 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pmo<15:0> 0000 90a0 ethrxfc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 hten mpen ? notpm pmmode<3:0> crc erren crc oken runt erren runten ucen not meen mcen bcen 0000 90b0 ethrxwm 31:16 ? ? ? ? ? ? ? ?rxfwm<7:0> 0000 15:0 ? ? ? ? ? ? ? ? rxewm<7:0> 0000 90c0 ethien 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? tx buseie rx buseie ? ? ? ew markie fw markie rx doneie pk tpendie rx actie ? tx doneie tx abortie rx bufnaie rx ovflwie 0000 90d0 ethirq 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? txbuse rxbuse ? ? ? ewmark fwmark rxdone pktpend rxact ? txdone txabort rxbufna rxovflw 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value.
? 2009-2013 microchip technology inc. ds60001156h-page 115 pic32mx5xx/6xx/7xx 90e0 ethstat 31:16 ? ? ? ? ? ? ? ? bufcnt<7:0> 0000 15:0 ? ? ? ? ? ? ? ? busy txbusy rxbusy ? ? ? ? ? 0000 9100 eth rxovflow 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rxovflwcnt<15:0> 0000 9110 eth frmtxok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 frmtxokcnt<15:0> 0000 9120 eth scolfrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 scolfrmcnt<15:0> 0000 9130 eth mcolfrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mcolfrmcnt<15:0> 0000 9140 eth frmrxok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 frmrxokcnt<15:0> 0000 9150 eth fcserr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 fcserrcnt<15:0> 0000 9160 eth algnerr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 algnerrcnt<15:0> 0000 9200 emac1 cfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 soft reset sim reset ? ? reset rmcs reset rfun reset tmcs reset tfun ? ? ? loopback txpause rxpause passall rxenable 800d 9210 emac1 cfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? excess dfr bp nobkoff nobkoff ? ? longpre purepre autopad vlanpad pad enable crc enable delaycrc hugefrm lengthck fulldplx 4082 9220 emac1 ipgt 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? b2bipktgp<6:0> 0012 9230 emac1 ipgr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? nb2bipktgp1<6:0> ? nb2bipktgp2<6:0> 0c12 9240 emac1 clrt 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cwindow<5:0> ? ? ? ?retx<3:0> 370f 9250 emac1 maxf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 macmaxf<15:0> 05ee table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, PIC32MX764F128L, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l d evices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value.
pic32mx5xx/6xx/7xx ds60001156h-page 116 ? 2009-2013 microchip technology inc. 9260 emac1 supp 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? reset rmii ? ? speed rmii ? ? ? ? ? ? ? ? 1000 9270 emac1 test 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? testbp testpause shrtqnta 0000 9280 emac1 mcfg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 reset mgmt ? ? ? ? ? ? ? ? ? clksel<3:0> nopre scaninc 0020 9290 emac1 mcmd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ?scanread 0000 92a0 emac1 madr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? phyaddr<4:0> ? ? ? regaddr<4:0> 0100 92b0 emac1 mwtd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mwtd<15:0> 0000 92c0 emac1 mrdd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mrdd<15:0> 0000 92d0 emac1 mind 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? linkfail notvalid scan miimbusy 0000 9300 emac1 sa0 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr6<7:0> stnaddr5<7:0> xxxx 9310 emac1 sa1 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr4<7:0> stnaddr3<7:0> xxxx 9320 emac1 sa2 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr2<7:0> stnaddr1<7:0> xxxx table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, PIC32MX764F128L, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l d evices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value.
? 2009-2013 microchip technology inc. ds60001156h-page 117 pic32mx5xx/6xx/7xx 4.2 control registers register 4-1 through register 4-8 are used for setting the ram and flash memory partitions for data and code. register 4-1: bmxcon: bus ma trix configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? bmx errixi bmx erricd bmx errdma bmx errds bmx erris 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 r/w-1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-1 ? bmx wsdrm ? ? ? bmxarb<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared bit 31-21 unimplemented: read as ? 0 ? bit 20 bmxerrixi: enable bus error from ixi bit 1 = enable bus error exceptions for unmapped address accesses initiated from ixi shared bus 0 = disable bus error exceptions for unmapped address accesses initiated from ixi shared bus bit 19 bmxerricd: enable bus error from icd debug unit bit 1 = enable bus error exceptions for unmapped address accesses initiated from icd 0 = disable bus error exceptions for unmapped address accesses initiated from icd bit 18 bmxerrdma: bus error from dma bit 1 = enable bus error exceptions for unmapped address accesses initiated from dma 0 = disable bus error exceptions for unmapped address accesses initiated from dma bit 17 bmxerrds: bus error from cpu data access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped address accesses initiated from cpu data access 0 = disable bus error exceptions for unmapped address accesses initiated from cpu data access bit 16 bmxerris: bus error from cpu instruction access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped addre ss accesses initiated from cpu instruction access 0 = disable bus error exceptions for unmapped addre ss accesses initiated from cpu instruction access bit 15-7 unimplemented: read as ? 0 ? bit 6 bmxwsdrm: cpu instruction or data access from data ram wait state bit 1 = data ram accesses from cpu have one wait state for address setup 0 = data ram accesses from cpu have zero wait states for address setup bit 5-3 unimplemented: read as ? 0 ? bit 2-0 bmxarb<2:0>: bus matrix arbitration mode bits 111 = reserved (using these configuration modes will produce undefined behavior) ? ? ? 011 = reserved (using these configuration modes will produce undefined behavior) 010 = arbitration mode 2 001 = arbitration mode 1 (default) 000 = arbitration mode 0
pic32mx5xx/6xx/7xx ds60001156h-page 118 ? 2009-2013 microchip technology inc. register 4-2: bmxdkpba: data ram ke rnel program base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdkpba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdkpba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdkpba<15:10>: drm kernel program base address bits when non-zero, this value selects the relative base address for kernel program space in ram bit 9-0 bmxdkpba<9:0>: drm kernel program base address read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
? 2009-2013 microchip technology inc. ds60001156h-page 119 pic32mx5xx/6xx/7xx register 4-3: bmxdudba: data ram user data base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdudba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdudba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdudba<15:10>: drm user data base address bits when non-zero, the value selects the relative base a ddress for user mode data space in ram, the value must be greater than bmxdkpba. bit 9-0 bmxdudba<9:0>: drm user data base address read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
pic32mx5xx/6xx/7xx ds60001156h-page 120 ? 2009-2013 microchip technology inc. register 4-4: bmxdupba: data ram user program base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdupba<15:10>: drm user program base address bits when non-zero, the value selects the relative base address for user mode program space in ram, bmxdupba must be greater than bmxdudba. bit 9-0 bmxdupba<9:0>: drm user program base address read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
? 2009-2013 microchip technology inc. ds60001156h-page 121 pic32mx5xx/6xx/7xx register 4-5: bmxdrmsz: data ram size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxdrmsz<31:24> 23:16 rrrrr r r r bmxdrmsz<23:16> 15:8 rrrrr r r r bmxdrmsz<15:8> 7:0 rrrrr r r r bmxdrmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxdrmsz<31:0>: data ram memory (drm) size bits static value that indicates the size of the data ram in bytes: 0x00004000 = device has 16 kb ram 0x00008000 = device has 32 kb ram 0x00010000 = device has 64 kb ram register 4-6: bmxpupba: program fla sh (pfm) user program base address register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bmxpupba<19:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxpupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxpupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-20 unimplemented: read as ? 0 ? bit 19-11 bmxpupba<19:11>: program flash (pfm) user program base address bits bit 10-0 bmxpupba<10:0>: program flash (pfm) user program base address read-only bits value is always ? 0 ?, which forces 2 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxpfmsz.
pic32mx5xx/6xx/7xx ds60001156h-page 122 ? 2009-2013 microchip technology inc. register 4-7: bmxpfmsz: program flash (pfm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxpfmsz<31:24> 23:16 rrrrr r r r bmxpfmsz<23:16> 15:8 rrrrr r r r bmxpfmsz<15:8> 7:0 rrrrr r r r bmxpfmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxpfmsz<31:0>: program flash memory (pfm) size bits static value that indicates the size of the pfm in bytes: 0x00010000 = device has 64 kb flash 0x00020000 = device has 128 kb flash 0x00040000 = device has 256 kb flash 0x00080000 = device has 512 kb flash register 4-8: bmxbootsz: boot flash (ifm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxbootsz<31:24> 23:16 rrrrr r r r bmxbootsz<23:16> 15:8 rrrrr r r r bmxbootsz<15:8> 7:0 rrrrr r r r bmxbootsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxbootsz<31:0>: boot flash memory (bfm) size bits static value that indicates the size of the boot pfm in bytes: 0x00003000 = device has 12 kb boot flash
? 2009-2013 microchip technology inc. ds60001156h-page 123 pic32mx5xx/6xx/7xx 5.0 flash program memory pic32mx5xx/6xx/7xx devices contain an internal flash program memory for ex ecuting user code. there are three methods by which the user can program this memory: ? run-time self-programming (rtsp) ? ejtag programming ? in-circuit serial programming? (icsp?) rtsp is performed by software executing from either flash or ram memory. information about rtsp techniques is available in section 5. ?flash program memory? (ds60001121) in the ?pic32 family reference manual?. ejtag is performed using the ejtag port of the device and an ejtag capable programmer. icsp is performed using a serial data connection to the device and allows much faster programming times than rtsp. the ejtag and icsp methods are described in the ? pic32 flash programming specification ? (ds60001145), which can be downloaded from the microchip web site. note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. ?flash program memory? (ds60001121) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: for pic32mx5xx/6xx/7xx devices, the flash page size is 4 kb and the row size is 512 bytes (1024 iw and 128 iw, respectively).
pic32mx5xx/6xx/7xx ds60001156h-page 124 ? 2009-2013 microchip technology inc. 5.1 control registers register 5-1: nvmcon: programming control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0, hc r/w-0 r-0, hs r-0, hs r-0, hsc u-0 u-0 u-0 wr wren wrerr (1) lvderr (1) lvdstat (1) ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? nvmop<3:0> legend: u = unimplemented bit, read as ?0? h sc = set and cleared by hardware r = readable bit w = writable bit hs = set by hardware hc = cleared by hardware -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 wr: write control bit this bit is writable when wren = 1 and the unlock sequence is followed. 1 = initiate a flash operation. hardware clears this bit when the operation completes 0 = flash operation complete or inactive bit 14 wren: write enable bit 1 = enable writes to wr bit and enables lvd circuit 0 = disable writes to wr bit and disables lvd circuit note: this is the only bit in this register that is reset by a device reset. bit 13 wrerr: write error bit (1) this bit is read-only and is automatically set by hardware. 1 = program or erase sequence did not complete successfully 0 = program or erase sequence completed normally bit 12 lvderr: low-voltage detect error bit (lvd circuit must be enabled) (1) this bit is read-only and is automatically set by hardware. 1 = low-voltage detected (possible data corruption, if wrerr is set) 0 = voltage level is acceptable for programming bit 11 lvdstat: low-voltage detect status bit (lvd circuit must be enabled) (1) this bit is read-only and is automatic ally set, and cleared, by hardware. 1 = low-voltage event is active 0 = low-voltage event is not active bit 10-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation bits these bits are writable when wren = 0 . 1111 = reserved ? ? ? 0111 = reserved 0110 = no operation 0101 = program flash (pfm) erase operation: erases pfm, if all pages are not write-protected 0100 = page erase operation: erases page selected by nvmaddr, if it is not write-protected 0011 = row program operation: programs row select ed by nvmaddr, if it is not write-protected 0010 = no operation 0001 = word program operation: programs word selected by nvmaddr, if it is not write-protected 0000 = no operation note 1: this bit is cleared by setting nvmop == 0000b , and initiating a flash operation (i.e., wr).
? 2009-2013 microchip technology inc. ds60001156h-page 125 pic32mx5xx/6xx/7xx register 5-2: nvmkey: programming unlock register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<31:24> 23:16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<23:16> 15:8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<15:8> 7:0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmkey<31:0>: unlock register bits these bits are write-only, and read as ? 0 ? on any read. note: this register is used as part of the unlock se quence to prevent inadvertent writes to the pfm. register 5-3: nvmaddr: flash address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmaddr<31:0>: flash address bits bulk/chip/pfm erase: address is ignored. page erase: address identifies the page to erase. row program: address identifies the row to program. word program: address identifies the word to program.
pic32mx5xx/6xx/7xx ds60001156h-page 126 ? 2009-2013 microchip technology inc. register 5-4: nvmdata: flash program data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmdata<31:0>: flash programming data bits note: the bits in this register are only reset by a power-on reset (por). register 5-5: nvmsrcaddr: source data address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmsrcaddr<31:0>: source data address bits the system physical address of th e data to be programmed into the flash when the nvmop<3:0> bits (nvmcon<3:0>) are set to perform row programming.
? 2009-2013 microchip technology inc. ds60001156h-page 127 pic32mx5xx/6xx/7xx 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the following is a list of device reset sources: ? power-on reset (por) ? master clear reset pin (mclr ) ? software reset (swr) ? watchdog timer reset (wdtr) ? brown-out reset (bor) ? configuration mismatch reset (cmr) a simplified block diagram of the reset module is illustrated in figure 6-1 . figure 6-1: system reset block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 7. ?resets? (ds60001118) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. mclr v dd v dd rise detect por sleep or idle brown-out reset wdt time-out glitch filter bor configuration sysrst software reset power-up timer voltage enabled reset wdtr swr cmr mclr mismatch regulator
pic32mx5xx/6xx/7xx ds60001156h-page 128 ? 2009-2013 microchip technology inc. 6.1 control registers register 6-1: rcon: re set control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0 ? ? ? ? ? ? cmr vregs 7:0 r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w- 0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr ? wdto sleep idle bor (1) por (1) legend: hs = set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-10 unimplemented: read as ? 0 ? bit 9 cmr: configuration mismatch reset flag bit 1 = configuration mismatch reset has occurred 0 = configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby enable bit 1 = regulator is enabled and is on during sleep mode 0 = regulator is disabled and is off during sleep mode bit 7 extr: external reset (mclr ) pin flag bit 1 = master clear (pin) reset has occurred 0 = master clear (pin) reset has not occurred bit 6 swr: software reset flag bit 1 = software reset was executed 0 = software reset was not executed bit 5 unimplemented: read as ? 0 ? bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device was in sleep mode 0 = device was not in sleep mode bit 2 idle: wake from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit (1) 1 = brown-out reset has occurred 0 = brown-out reset has not occurred bit 0 por: power-on reset flag bit (1) 1 = power-on rese t has occurred 0 = power-on reset has not occurred note 1: user software must clear this bit to view the next detection.
? 2009-2013 microchip technology inc. ds60001156h-page 129 pic32mx5xx/6xx/7xx register 6-2: rswrst: software reset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 w-0, hc ? ? ? ? ? ? ?swrst (1) legend: hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as ? 0 ? bit 0 swrst: software reset trigger bit (1) 1 = enable software reset event 0 = no effect note 1: the system unlock sequence must be performed be fore the swrst bit can be written. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx5xx/6xx/7xx ds60001156h-page 130 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 131 pic32mx5xx/6xx/7xx 7.0 interrupt controller pic32mx5xx/6xx/7xx devices generate interrupt requests in response to inte rrupt events from peripheral modules. the interrupt cont rol module exists externally to the cpu logic and prioritizes the interrupt events before presenting them to the cpu. the interrupt controller module includes the following features: ? up to 96 interrupt sources ? up to 64 interrupt vectors ? single and multi-vector mode operations ? five external interrupts with edge polarity control ? interrupt proximity timer ? seven user-selectable priority levels for each vector ? four user-selectable subpriority levels within each priority ? dedicated shadow set for user-selectable priority level ? software can generate any interrupt ? user-configurable interrupt vector table location ? user-configurable interrupt vector spacing a simplified block diagram of the interrupt controller module is illustrated in figure 7-1 . figure 7-1: interrupt controller module note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?interrupts? (ds60001108) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. interrupt controller interrupt requests vector number cpu core priority level shadow set number
pic32mx5xx/6xx/7xx ds60001156h-page 132 ? 2009-2013 microchip technology inc. table 7-1: interrupt irq, vector and bit location interrupt source (1) irq number vector number interrupt bit location flag enable priority sub-priority highest natural order priority ct ? core timer interrupt 0 0 ifs0<0> iec0<0> ipc0<4:2> ipc0<1:0> cs0 ? core software interrupt 0 1 1 ifs0<1> iec0<1> ipc0<12:10> ipc0<9:8> cs1 ? core software interrupt 1 2 2 ifs0<2> iec0<2> ipc0<20:18> ipc0<17:16> int0 ? external interrupt 0 3 3 ifs0<3> iec0<3> ipc0<28:26> ipc0<25:24> t1 ? timer1 4 4 ifs0<4> iec0<4> ipc1<4:2> ipc1<1:0> ic1 ? input capture 1 5 5 ifs0<5> iec0<5> ipc1<12:10> ipc1<9:8> oc1 ? output compare 1 6 6 ifs0<6> iec0<6> ipc1<20:18> ipc1<17:16> int1 ? external interrupt 1 7 7 ifs0<7> iec0<7> ipc1<28:26> ipc1<25:24> t2 ? timer2 8 8 ifs0<8> iec0<8> ipc2<4:2> ipc2<1:0> ic2 ? input capture 2 9 9 ifs0<9> iec0<9> ipc2<12:10> ipc2<9:8> oc2 ? output compare 2 10 10 ifs0<10> iec0<10> ipc2<20:18> ipc2<17:16> int2 ? external interrupt 2 11 11 ifs0<11> iec0<11> ipc2<28:26> ipc2<25:24> t3 ? timer3 12 12 ifs0<12> iec0<12> ipc3<4:2> ipc3<1:0> ic3 ? input capture 3 13 13 ifs0<13> iec0<13> ipc3<12:10> ipc3<9:8> oc3 ? output compare 3 14 14 ifs0<14> iec0<14> ipc3<20:18> ipc3<17:16> int3 ? external interrupt 3 15 15 ifs0<15> iec0<15> ipc3<28:26> ipc3<25:24> t4 ? timer4 16 16 ifs0<16> iec0<16> ipc4<4:2> ipc4<1:0> ic4 ? input capture 4 17 17 ifs0<17> iec0<17> ipc4<12:10> ipc4<9:8> oc4 ? output compare 4 18 18 ifs0<18> iec0<18> ipc4<20:18> ipc4<17:16> int4 ? external interrupt 4 19 19 ifs0<19> iec0<19> ipc4<28:26> ipc4<25:24> t5 ? timer5 20 20 ifs0<20> iec0<20> ipc5<4:2> ipc5<1:0> ic5 ? input capture 5 21 21 ifs0<21> iec0<21> ipc5<12:10> ipc5<9:8> oc5 ? output compare 5 22 22 ifs0<22> iec0<22> ipc5<20:18> ipc5<17:16> spi1e ? spi1 fault 23 23 ifs0<23> iec0<23> ipc5<28:26> ipc5<25:24> spi1rx ? spi1 receive done 24 23 ifs0<24> iec0<24> ipc5<28:26> ipc5<25:24> spi1tx ? spi1 transfer done 25 23 ifs0<25> iec0<25> ipc5<28:26> ipc5<25:24> u1e ? uart1 error 26 24 ifs0<26> iec0<26> ipc6<4:2> ipc6<1:0> spi3e ? spi3 fault i2c3b ? i2c3 bus collision event u1rx ? uart1 receiver 27 24 ifs0<27> iec0<27> ipc6<4:2> ipc6<1:0> spi3rx ? spi3 receive done i2c3s ? i2c3 slave event u1tx ? uart1 transmitter 28 24 ifs0<28> iec0<28> ipc6<4:2> ipc6<1:0> spi3tx ? spi3 transfer done i2c3m ? i2c3 master event i2c1b ? i2c1 bus collision event 29 25 ifs0<29> iec0<29> ipc6<12:10> ipc6<9:8> i2c1s ? i2c1 slave event 30 25 ifs0<30> iec0<30> ipc6<12:10> ipc6<9:8> i2c1m ? i2c1 master event 31 25 ifs0<31> iec0<31> ipc6<12:10> ipc6<9:8> cn ? input change interrupt 32 26 ifs1<0> iec1<0> ipc6<20:18> ipc6<17:16> note 1: not all interrupt sources are available on all devices. see table 1: ?pic32 usb and can ? features? , table 2: ?pic32 usb and ethernet ? features? and table 3: ?pic32 usb, ethernet and can ? features? for the list of available peripherals.
? 2009-2013 microchip technology inc. ds60001156h-page 133 pic32mx5xx/6xx/7xx ad1 ? adc1 convert done 33 27 ifs1<1> iec1<1> ipc6<28:26> ipc6<25:24> pmp ? parallel master port 34 28 ifs1<2> iec1<2> ipc7<4:2> ipc7<1:0> cmp1 ? comparator interrupt 35 29 ifs1<3> iec1<3> ipc7<12:10> ipc7<9:8> cmp2 ? comparator interrupt 36 30 ifs1<4> iec1<4> ipc7<20:18> ipc7<17:16> u3e ? uart2a error spi2e ? spi2 fault i2c4b ? i2c4 bus collision event 37 31 ifs1<5> iec1<5> ipc7<28:26> ipc7<25:24> u3rx ? uart2a receiver spi2rx ? spi2 receive done i2c4s ? i2c4 slave event 38 31 ifs1<6> iec1<6> ipc7<28:26> ipc7<25:24> u3tx ? uart2a transmitter spi2tx ? spi2 transfer done ic4m ? i2c4 master event 39 31 ifs1<7> iec1<7> ipc7<28:26> ipc7<25:24> u2e ? uart3a error spi4e ? spi4 fault i2c5b ? i2c5 bus collision event 40 32 ifs1<8> iec1<8> ipc8<4:2> ipc8<1:0> u2rx ? uart3a receiver spi4rx ? spi4 receive done i2c5s ? i2c5 slave event 41 32 ifs1<9> iec1<9> ipc8<4:2> ipc8<1:0> u2tx ? uart3a transmitter spi4tx ? spi4 transfer done ic5m ? i2c5 master event 42 32 ifs1<10> iec1<10> ipc8<4:2> ipc8<1:0> i2c2b ? i2c2 bus collision event 43 33 ifs1<11> iec1<11> ipc8<12:10> ipc8<9:8> i2c2s ? i2c2 slave event 44 33 ifs1<12> iec1<12> ipc8<12:10> ipc8<9:8> i2c2m ? i2c2 master event 45 33 ifs1<13> iec1<13> ipc8<12:10> ipc8<9:8> fscm ? fail-safe clock monitor 46 34 ifs1<14> iec1<14> ipc8<20:18> ipc8<17:16> rtcc ? real-time clock and calendar 47 35 ifs1<15> iec1<15> ipc8<28:26> ipc8<25:24> dma0 ? dma channel 0 48 36 ifs1<16> iec1<16> ipc9<4:2> ipc9<1:0> dma1 ? dma channel 1 49 37 ifs1<17> iec1<17> ipc9<12:10> ipc9<9:8> dma2 ? dma channel 2 50 38 ifs1<18> iec1<18> ipc9<20:18> ipc9<17:16> dma3 ? dma channel 3 51 39 ifs1<19> iec1<19> ipc9<28:26> ipc9<25:24> dma4 ? dma channel 4 52 40 ifs1<20> iec1<20> ipc10<4:2> ipc10<1:0> dma5 ? dma channel 5 53 41 ifs1<21> iec1<21> ipc10<12:10> ipc10<9:8> dma6 ? dma channel 6 54 42 ifs1<22> iec1<22> ipc10<20:18> ipc10<17:16> dma7 ? dma channel 7 55 43 ifs1<23> iec1<23> ipc10<28:26> ipc10<25:24> fce ? flash control event 56 44 ifs1<24> iec1<24> ipc11<4:2> ipc11<1:0> usb ? usb interrupt 57 45 ifs1<25> iec1<25> ipc11<12:10> ipc11<9:8> can1 ? control area network 1 58 46 ifs1<26> iec1<26> ipc11<20:18> ipc11<17:16> can2 ? control area network 2 59 47 ifs1<27> iec1<27> ipc11<28:26> ipc11<25:24> eth ? ethernet interrupt 60 48 ifs1<28> iec1<28> ipc12<4:2> ipc12<1:0> ic1e ? input capture 1 error 61 5 ifs1<29> iec1<29> ipc1<12:10> ipc1<9:8> ic2e ? input capture 2 error 62 9 ifs1<30> iec1<30> ipc2<12:10> ipc2<9:8> table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq number vector number interrupt bit location flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: ?pic32 usb and can ? features? , table 2: ?pic32 usb and ethernet ? features? and table 3: ?pic32 usb, ethernet and can ? features? for the list of available peripherals.
pic32mx5xx/6xx/7xx ds60001156h-page 134 ? 2009-2013 microchip technology inc. ic3e ? input capture 3 error 63 13 ifs1<31> iec1<31> ipc3<12:10> ipc3<9:8> ic4e ? input capture 4 error 64 17 ifs2<0> iec2<0> ipc4<12:10> ipc4<9:8> ic4e ? input capture 5 error 65 21 ifs2<1> iec2<1> ipc5<12:10> ipc5<9:8> pmpe ? parallel master port error 6 6 28 ifs2<2> iec2<2> ipc7<4:2> ipc7<1:0> u4e ? uart4 error 67 49 ifs2<3> iec2<3> ipc12<12:10> ipc12<9:8> u4rx ? uart4 receiver 68 49 ifs2<4> iec2<4> ipc12<12:10> ipc12<9:8> u4tx ? uart4 transmitter 69 49 ifs2<5> iec2<5> ipc12<12:10> ipc12<9:8> u6e ? uart6 error 70 50 ifs2<6> iec2<6> ipc12<20:18> ipc12<17:16> u6rx ? uart6 receiver 71 50 ifs2<7> iec2<7> ipc12<20:18> ipc12<17:16> u6tx ? uart6 transmitter 72 50 ifs2<8> iec2<8> ipc12<20:18> ipc12<17:16> u5e ? uart5 error 73 51 ifs2<9> iec2<9> ipc12<28:26> ipc12<25:24> u5rx ? uart5 receiver 74 51 ifs2<10> iec2<10> ipc12<28:26> ipc12<25:24> u5tx ? uart5 transmitter 75 51 ifs2<11> iec2<11> ipc12<28:26> ipc12<25:24> (reserved) ? ? ? ? ? ? lowest natural order priority table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq number vector number interrupt bit location flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: ?pic32 usb and can ? features? , table 2: ?pic32 usb and ethernet ? features? and table 3: ?pic32 usb, ethernet and can ? features? for the list of available peripherals.
? 2009-2013 microchip technology inc. ds60001156h-page 135 pic32mx5xx/6xx/7xx 7.1 control registers register 7-1: intcon: interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ss0 15:8 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? mvec ?tpc<2:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-17 unimplemented: read as ? 0 ? bit 16 ss0: single vector shadow register set bit 1 = single vector is presented with a shadow register set 0 = single vector is not presented with a shadow register set bit 15-13 unimplemented: read as ? 0 ? bit 12 mvec: multiple vector configuration bit 1 = interrupt controller confi gured for multi-vector mode 0 = interrupt controller configured for single-vector mode bit 11 unimplemented: read as ? 0 ? bit 10-8 tpc<2:0>: interrupt proximity timer control bits 111 = interrupts of group priority 7 or lo wer start the interrupt proximity timer 110 = interrupts of group priority 6 or lo wer start the interrupt proximity timer 101 = interrupts of group priority 5 or lo wer start the interrupt proximity timer 100 = interrupts of group priority 4 or lo wer start the interrupt proximity timer 011 = interrupts of group priority 3 or lo wer start the interrupt proximity timer 010 = interrupts of group priority 2 or lo wer start the interrupt proximity timer 001 = interrupts of group priority 1 start the interrupt proximity timer 000 = disables interrupt proximity timer bit 7-5 unimplemented: read as ? 0 ? bit 4 int4ep: external interrupt 4 edge polarity control bit 1 = rising edge 0 = falling edge bit 3 int3ep: external interrupt 3 edge polarity control bit 1 = rising edge 0 = falling edge bit 2 int2ep: external interrupt 2 edge polarity control bit 1 = rising edge 0 = falling edge bit 1 int1ep: external interrupt 1 edge polarity control bit 1 = rising edge 0 = falling edge bit 0 int0ep: external interrupt 0 edge polarity control bit 1 = rising edge 0 = falling edge
pic32mx5xx/6xx/7xx ds60001156h-page 136 ? 2009-2013 microchip technology inc. register 7-2: intstat: interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ripl<2:0> (1) 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vec<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as ? 0 ? bit 10-8 ripl<2:0>: requested priority level bits (1) 111-000 = the priority level of the late st interrupt presented to the cpu bit 7-6 unimplemented: read as ? 0 ? bit 5-0 vec<5:0>: interrupt vector bits (1) 11111-00000 = the interrupt vector that is presented to the cpu note 1: this value should only be used when the interr upt controller is configured for single-vector mode. register 7-3: tptmr: temporal proximity timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 tptmr<31:0>: temporal proximity timer reload bits used by the temporal proximity timer as a reload valu e when the temporal proximity timer is triggered by an interrupt event.
? 2009-2013 microchip technology inc. ds60001156h-page 137 pic32mx5xx/6xx/7xx register 7-4: ifsx: interru pt flag status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs31 ifs30 ifs29 ifs28 ifs27 ifs26 ifs25 ifs24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs23 ifs22 ifs21 ifs20 ifs19 ifs18 ifs17 ifs16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs15 ifs14 ifs13 ifs12 ifs11 ifs10 ifs09 ifs08 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs07 ifs06 ifs05 ifs04 ifs03 ifs02 ifs01 ifs00 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 ifs31-ifs00: interrupt flag status bits 1 = interrupt request has occurred 0 = interrupt request has not occurred note: this register represents a generic defin ition of the ifsx register. refer to ta b l e 7 - 1 for the exact bit definitions. register 7-5: iecx: interrupt enable control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec31 iec30 iec29 iec28 iec27 iec26 iec25 iec24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec23 iec22 iec21 iec20 iec19 iec18 iec17 iec16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec15 iec14 iec13 iec12 iec11 iec10 iec09 iec08 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec07 iec06 iec05 iec04 iec03 iec02 iec01 iec00 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 iec31-iec00: interrupt enable bits 1 = interrupt is enabled 0 = interrupt is disabled note: this register represents a generic defin ition of the iecx register. refer to ta b l e 7 - 1 for the exact bit definitions.
pic32mx5xx/6xx/7xx ds60001156h-page 138 ? 2009-2013 microchip technology inc. register 7-6: ipcx: interrupt priority control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip03<2:0> is03<1:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip02<2:0> is02<1:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip01<2:0> is01<1:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip00<2:0> is00<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-26 ip03<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 is03<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpiority is 0 bit 23-21 unimplemented: read as ? 0 ? bit 20-18 ip02<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 is02<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 15-13 unimplemented: read as ? 0 ? note: this register represents a generic defin ition of the ipcx register. refer to ta b l e 7 - 1 for the exact bit definitions.
? 2009-2013 microchip technology inc. ds60001156h-page 139 pic32mx5xx/6xx/7xx bit 12-10 ip01<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 is01<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-2 ip00<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 is00<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 7-6: ipcx: interrupt priority control register (continued) note: this register represents a generic defin ition of the ipcx register. refer to ta b l e 7 - 1 for the exact bit definitions.
pic32mx5xx/6xx/7xx ds60001156h-page 140 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 141 pic32mx5xx/6xx/7xx 8.0 oscillator configuration the oscillator module has the following features: ? a total of four external and internal oscillator options as clock sources ? on-chip pll with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources ? on-chip user-selectable divisor postscaler on select oscillator sources ? software-controllable switching between various clock sources ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown ? dedicated on-chip pll for usb peripheral figure 8-1 shows the oscillator module block diagram. figure 8-1: oscillator block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. timer1, rtcc clock control logic fail-safe clock monitor fscm int fscm event cosc<2:0> nosc<2:0> oswen fscmen<1:0> pll secondary oscillator (s osc ) soscen and fsoscen sosco sosci xtpll, hspll, xt, hs, ec cpu and select peripherals peripherals frcdiv<2:0> wdt, pwrt 8 mhz typical frc 31.25 khz typical frc oscillator lprc oscillator s osc lprc frcdiv ecpll, frcpll tun<5:0> div 16 postscaler fpllidiv<2:0> pbdiv<1:0> frc/16 postscaler pll multiplier cosc<2:0> f in div x div y pll output divider pllodiv<2:0> pll input divider div x 32.768 khz pllmult<2:0> pbclk uf in ?? 4 mhz pll x24 usb clock (48 mhz) div 2 upllen ufrcen div x upllidiv<2:0> uf in 4 mhz ? f in ? 5 mhz usb pll sysclk primary oscillator c1 (3) c2 (3) xtal r s (1) enable osc2 (4) osc1 r f (2) to internal logic (p osc ) r p (1) notes: 1. a series resistor, r s , may be required for at strip cut crystals or eliminate clipping. alternately, to increase oscillator circuit gain, add a parallel resistor, r p , with a value of 1 m ?? 2. the internal feedback resistor, r f , is typically in the range of 2 to 10 m ?? 3. refer to the ? pic32 family reference manual ? section 6. ?oscillator configuration? (ds60001112) for help determining the best oscillator components. 4. pbclk out is available on the osc2 pin in certain clock modes.
pic32mx5xx/6xx/7xx ds60001156h-page 142 ? 2009-2013 microchip technology inc. 8.1 control registers register 8-1: osccon: os cillator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-y r/w-y r/w-y r/w-0 r/w-0 r/w-1 ? ? pllodiv<2:0> frcdiv<2:0> 23:16 u-0 r-0 r-1 r/w-y r/w-y r/w-y r/w-y r/w-y ? soscrdy pbdivrdy pbdiv<1:0> pllmult<2:0> 15:8 u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc<2:0> ? nosc<2:0> 7:0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-y r/w-0 clklock ulock slock slpen cf ufrcen soscen oswen legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-27 pllodiv<2:0>: output divider for pll 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 26-24 frcdiv<2:0>: internal fast rc (frc) oscillator clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default setting) 000 = frc divided by 1 bit 23 unimplemented: read as ? 0 ? bit 22 soscrdy: secondary oscillator (s osc ) ready indicator bit 1 = indicates that the secondary oscillator is running and is stable 0 = secondary oscillator is still warming up or is turned off bit 21 pbdivrdy: peripheral bus clock (pbclk) divisor ready bit 1 = pbdiv<1:0> bits can be written 0 = pbdiv<1:0> bits cannot be written bit 20-19 pbdiv<1:0>: peripheral bus clock (pbclk) divisor bits 11 = pbclk is sysclk divided by 8 (default) 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
? 2009-2013 microchip technology inc. ds60001156h-page 143 pic32mx5xx/6xx/7xx bit 18-16 pllmult<2:0>: phase-locked loop (pll) multiplier bits 111 = clock is multiplied by 24 110 = clock is multiplied by 21 101 = clock is multiplied by 20 100 = clock is multiplied by 19 011 = clock is multiplied by 18 010 = clock is multiplied by 17 001 = clock is multiplied by 16 000 = clock is multiplied by 15 bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits 111 = internal fast rc (frc) oscillat or divided by osccon bits 110 = internal fast rc (frc) oscillator divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (p osc ) (xt, hs or ec) 001 = internal fast rc oscillator with pll module via postscaler (frcpll) 000 = internal fast rc (frc) oscillator bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits 111 = internal fast rc oscillator (f rc) divided by osccon bits 110 = internal fast rc osc illator (frc) divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = internal fast internal rc oscillator with pll module via postscaler (frcpll) 000 = internal fast internal rc oscillator (frc) on reset, these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit if clock switching and monitoring is disabled ( fcksm<1:0> = 1x ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified if clock switching and monitoring is enabled (fcksm<1:0> = 0x ): clock and pll selections are never locked and may be modified. bit 6 ulock: usb pll lock status bit 1 = indicates that the usb pll module is in lock or usb pll module start-up timer is satisfied 0 = indicates that the usb pll module is out of lock or usb pll module start-up timer is in progress or usb pll is disabled bit 5 slock: pll lock status bit 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected register 8-1: osccon: oscillator control register (continued) note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx5xx/6xx/7xx ds60001156h-page 144 ? 2009-2013 microchip technology inc. bit 2 ufrcen: usb frc clock enable bit 1 = enable frc as the clock so urce for the usb clock source 0 = use the primary oscillator or usb pll as the usb clock source bit 1 soscen: secondary oscillator (s osc ) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: oscillator control register (continued) note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
? 2009-2013 microchip technology inc. ds60001156h-page 145 pic32mx5xx/6xx/7xx register 8-2: osctun: frc tuning register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 100000 = center frequency -12.5% 100001 = ? ? ? 111111 = 000000 = center frequency; oscillator ru ns at minimal frequency (8 mhz) 000001 = ? ? ? 011110 = 011111 = center frequency +12.5% note 1: osctun functionality has been provided to help customers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tuning step size is an approximation, and is neither characterized, nor tested. note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx5xx/6xx/7xx ds60001156h-page 146 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 147 pic32mx5xx/6xx/7xx 9.0 prefetch cache prefetch cache increases performance for applications executing out of the cacheable program flash memory regions by implementing inst ruction caching, constant data caching and instruction prefetching. 9.1 features ? 16 fully-associative lockable cache lines ? 16-byte cache lines ? up to four cache lines allocated to data ? two cache lines with address mask to hold repeated instructions ? pseudo-lru replacement policy ? all cache lines are software writable ? 16-byte parallel memory fetch ? predictive instruction prefetch a simplified block diagram of the prefetch cache module is illustrated in figure 9-1 . figure 9-1: prefetch cache module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. ?prefetch cache? (ds60001119) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. ctrl rdata prefetch prefetch hit logic cache line address encode cache line fsm ctrl rdata tag logic bus control cache control prefetch control hit lru miss lru bmx/cpu bmx/cpu ctrl pfm
pic32mx5xx/6xx/7xx ds60001156h-page 148 ? 2009-2013 microchip technology inc. 9.2 control registers register 9-1: checon: cache control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? checoh 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? dcsz<1:0> 7:0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ? ? prefen<1:0> ?pfmws<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-17 unimplemented: write ? 0 ?; ignore read bit 16 checoh: cache coherency setting on a pfm program cycle bit 1 = invalidate all data and instruction lines 0 = invalidate all data lnes and in struction lines that are not locked bit 15-10 unimplemented: write ? 0 ?; ignore read bit 9-8 dcsz<1:0>: data cache size in lines bits changing these bits causes all lines to be reinitialized to the ?invalid? state. 11 = enable data caching with a size of 4 lines 10 = enable data caching with a size of 2 lines 01 = enable data caching with a size of 1 line 00 = disable data caching bit 7-6 unimplemented: write ? 0 ?; ignore read bit 5-4 prefen<1:0>: predictive prefetch enable bits 11 = enable predictive prefetch for both cacheable and non-cacheable regions 10 = enable predictive prefetch only for non-cacheable regions 01 = enable predictive prefetch only for cacheable regions 00 = disable predictive prefetch bit 3 unimplemented: write ? 0 ?; ignore read bit 2-0 pfmws<2:0>: pfm access time defined in terms of syslk wait states bits 111 = seven wait states 110 = six wait states 101 = five wait states 100 = four wait states 011 = three wait states 010 = two wait states 001 = one wait state 000 = zero wait state
? 2009-2013 microchip technology inc. ds60001156h-page 149 pic32mx5xx/6xx/7xx register 9-2: cheacc: cache access register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 chewen ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? cheidx<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 chewen: cache access enable bits these bits apply to registers chetag, chemsk, chew0, chew1, chew2, and chew3. 1 = the cache line selected by cheidx<3:0> is writeable 0 = the cache line selected by cheidx<3:0> is not writeable bit 30-4 unimplemented: write ? 0 ?; ignore read bit 3-0 cheidx<3:0>: cache line index bits the value selects the cache line for reading or writing.
pic32mx5xx/6xx/7xx ds60001156h-page 150 ? 2009-2013 microchip technology inc. register 9-3: chetag: cache tag register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ltagboot ? ? ? ? ? ? ? 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<19:12> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<11:4> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-0 r/w-0 r/w-1 u-0 ltag<3:0> lvalid llock ltype ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ltagboot: line tag address boot bit 1 = the line is in the 0x1d000000 (physical) area of memory 0 = the line is in the 0x1fc00000 (physical) area of memory bit 30-24 unimplemented: write ? 0 ?; ignore read bit 23-4 ltag<19:0>: line tag address bits ltag<19:0> bits are compared against physical address to determine a hit. because its address range and position of pfm in kernel space and user space, the ltag pfm address is identical for virtual addresses, (system) physical addresses, and pfm physical addresses. bit 3 lvalid: line valid bit 1 = the line is valid and is compared to the physical address for hit detection 0 = the line is not valid and is not compared to the physical address for hit detection bit 2 llock: line lock bit 1 = the line is locked and will not be replaced 0 = the line is not locked and can be replaced bit 1 ltype: line type bit 1 = the line caches instruction words 0 = the line caches data words bit 0 unimplemented: write ? 0 ?; ignore read
? 2009-2013 microchip technology inc. ds60001156h-page 151 pic32mx5xx/6xx/7xx register 9-4: chemsk: c ache tag mask register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lmask<10:3> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 lmask<2:0> ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: write ? 0 ?; ignore read bit 15-5 lmask<10:0>: line mask bits 1 = enables mask logic to force a match on the corresponding bit position in ltag<19:0> bits (chetag<23:4>) and the physical address 0 = only writeable for values of cheidx<3:0> bits (cheacc<3:0>) equal to 0x0a and 0x0b (disables mask logic) bit 4-0 unimplemented: write ? 0 ?; ignore read register 9-5: chew0: cache word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew0<31:0>: word 0 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected.
pic32mx5xx/6xx/7xx ds60001156h-page 152 ? 2009-2013 microchip technology inc. register 9-6: chew1: cache word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew1<31:0>: word 1 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected. register 9-7: chew2: cache word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew2<31:0>: word 2 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected.
? 2009-2013 microchip technology inc. ds60001156h-page 153 pic32mx5xx/6xx/7xx register 9-8: chew3: cache word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew3<31:0>: word 3 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected. note: this register is a window into the cache data array and is only readable if the dev ice is not code-protected. register 9-9: chelru: cache lru register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ? chelru<24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-25 unimplemented: write ? 0 ?; ignore read bit 24-0 chelru<24:0>: cache least recently used state encoding bits indicates the pseudo-lru state of the cache.
pic32mx5xx/6xx/7xx ds60001156h-page 154 ? 2009-2013 microchip technology inc. register 9-10: chehit: cache hit statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chehit<31:0>: cache hit count bits incremented each time the processor issues an instructio n fetch or load that hits the prefetch cache from a cacheable region. non-cacheable accesses do not modify this value. register 9-11: chemis: cach e miss statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chemis<31:0>: cache miss count bits incremented each time the processor is sues an instruction fetch from a cacheable region that misses the prefetch cache. non-cacheable acce sses do not modify this value.
? 2009-2013 microchip technology inc. ds60001156h-page 155 pic32mx5xx/6xx/7xx register 9-12: chepfabt: prefetch cache abort statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chepfabt<31:0>: prefab abort count bits incremented each time an automatic pref etch cache is aborted due to a no n-sequential instruction fetch, load or store.
pic32mx5xx/6xx/7xx ds60001156h-page 156 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 157 pic32mx5xx/6xx/7xx 10.0 direct memory access (dma) controller the direct memory access (dma) controller is a bus master module useful for data transfers between different devices without cpu intervention. the source and destination of a dma transfer can be any of the memory mapped modules exis tent in the pic32 (such as spi, uart, pmp, etc.) or memory itself. following are some of the key features of the dma controller module: ? four identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers - memory to memory and memory to peripheral transfers ? automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination ? fixed priority channel arbitration ? flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repeat block transfer modes - channel-to-channel chaining ? flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - pattern (data) match transfer termination ? multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half full - dma transfer aborted due to an external event - invalid dma address generated ? dma debug support features: - most recent address accessed by a dma channel - most recent dma channel to transfer data ? crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable figure 10-1: dma block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 31. ?direct memory access (dma) controller? (ds60001117) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. address decoder channel 0 control channel 1 control channel ?n? control global control (dmacon) bus interface channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq int controller device bus + bus arbitration peripheral bus
pic32mx5xx/6xx/7xx ds60001156h-page 158 ? 2009-2013 microchip technology inc. 10.1 control registers register 10-1: dmacon: dma co ntroller control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 on (1) ? ? suspend dmabusy ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: dma on bit (1) 1 = dma module is enabled 0 = dma module is disabled bit 14-13 unimplemented: read as ? 0 ? bit 12 suspend: dma suspend bit 1 = dma transfers are suspended to allow cpu uninterrupted access to data bus 0 = dma operates normally bit 11 dmabusy: dma module busy bit 1 = dma module is active 0 = dma module is disabled and not actively transferring data bit 10-0 unimplemented: read as ? 0 ? note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2009-2013 microchip technology inc. ds60001156h-page 159 pic32mx5xx/6xx/7xx register 10-2: dmastat: dma status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? rdwr dmach<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 rdwr: read/write status bit 1 = last dma bus access was a read 0 = last dma bus access was a write bit 2-0 dmach<2:0>: dma channel bits these bits contain the value of the most recent active dma channel. register 10-3: dmaaddr: dma address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dmaaddr<31:0>: dma module address bits these bits contain the address of the most recent dma access.
pic32mx5xx/6xx/7xx ds60001156h-page 160 ? 2009-2013 microchip technology inc. register 10-4: dcrccon: dm a crc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 ? ?byto<1:0>wbo (1) ? ?bito 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen<4:0> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 crcen crcapp (1) crctyp ? ? crcch<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-28 byto<1:0>: crc byte order selection bits 11 = endian byte swap on half-word boundaries (source half-word order with reverse source byte order per half-word) 10 = swap half-words on word boundaries (reverse source half-word order with source byte order per half-word) 01 = endian byte swap on word boundaries (reverse source byte order) 00 = no swapping (source byte order) bit 27 wbo: crc write byte order selection bit (1) 1 = source data is written to the destina tion re-ordered as defined by byto<1:0> 0 = source data is written to the destination unaltered bit 26-25 unimplemented: read as ? 0 ? bit 24 bito: crc bit order selection bit when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): 1 = the ip header checksum is calculated least significant bit (lsb) first (reflected) 0 = the ip header checksum is calculated most significant bit (msb) first (not reflected) when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = the lfsr crc is calculated least significant bit first (reflected) 0 = the lfsr crc is calculated most significant bit first (not reflected) bit 23-13 unimplemented: read as ? 0 ? bit 12-8 plen<4:0>: polynomial length bits (1) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): these bits are unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): denotes the length of the polynomial ? 1. bit 7 crcen: crc enable bit 1 = crc module is enabled and channel transfers are routed through the crc module 0 = crc module is disabled and channel transfers proceed normally note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set.
? 2009-2013 microchip technology inc. ds60001156h-page 161 pic32mx5xx/6xx/7xx bit 6 crcapp: crc append mode bit (1) 1 = the dma transfers data from the source into th e crc but not to the destination. when a block transfer completes the dma writes the calculated crc value to the location given by chxdsa 0 = the dma transfers data from the source through the crc obeying wbo as it writes the data to the destination bit 5 crctyp: crc type selection bit 1 = the crc module will calculate an ip header checksum 0 = the crc module will calculate a lfsr crc bit 4-3 unimplemented: read as ? 0 ? bit 2-0 crcch<2:0>: crc channel select bits 111 = crc is assigned to channel 7 110 = crc is assigned to channel 6 101 = crc is assigned to channel 5 100 = crc is assigned to channel 4 011 = crc is assigned to channel 3 010 = crc is assigned to channel 2 001 = crc is assigned to channel 1 000 = crc is assigned to channel 0 register 10-4: dcrccon: dma crc control register (continued) note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set.
pic32mx5xx/6xx/7xx ds60001156h-page 162 ? 2009-2013 microchip technology inc. register 10-5: dcrcdata: dma crc data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcdata<31:0>: crc data register bits writing to this register will seed t he crc generator. reading from this regi ster will return the current value of the crc. bits greater than plen will return ? 0 ? on any read. when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): only the lower 16 bits contain ip header checksum information. the upper 16 bits are always ? 0 ?. data written to this register is conv erted and read back in 1?s complement fo rm (current ip header checksum value). when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): bits greater than plen will return ? 0 ? on any read. register 10-6: dcrcxor: dma crcxor enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcxor<31:0>: crc xor register bits when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): this register is unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = enable the xor input to the shift register 0 = disable the xor input to the shift register; data is shifted in directly from the previous stage in the register
? 2009-2013 microchip technology inc. ds60001156h-page 163 pic32mx5xx/6xx/7xx register 10-7: dchxcon: dma channel ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 chbusy ? ? ? ? ? ? chchns (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r/w-0 chen (2) chaed chchn chaen ? chedet chpri<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 chbusy: channel busy bit 1 = channel is active or has been enabled 0 = channel is inactive or has been disabled bit 14-9 unimplemented: read as ? 0 ? bit 8 chchns: chain channel selection bit (1) 1 = chain to channel lower in natural priority (ch1 will be enabled by ch2 transfer complete) 0 = chain to channel higher in natural priority (ch1 will be enabled by ch0 transfer complete) bit 7 chen: channel enable bit (2) 1 = channel is enabled 0 = channel is disabled bit 6 chaed: channel allow events if disabled bit 1 = channel start/abort events will be regi stered, even if the channel is disabled 0 = channel start/abort events will be ignored if the channel is disabled bit chchn: channel chain enable bit 1 = allow channel to be chained 0 = do not allow channel to be chained bit 4 chaen: channel automatic enable bit 1 = channel is continuously enabled, and not automat ically disabled after a block transfer is complete 0 = channel is disabled on block transfer complete bit 3 unimplemented: read as ? 0 ? bit 2 chedet: channel event detected bit 1 = an event has been detected 0 = no events have been detected bit 1-0 chpri<1:0>: channel priority bits 11 = channel has priority 3 (highest) 10 = channel has priority 2 01 = channel has priority 1 00 = channel has priority 0 note 1: the chain selection bit takes effect when chaining is enabled (chchn = 1 ). 2: when the channel is suspended by clearing this bit, the user application should poll the chbusy bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transacti on before the channel is suspended.
pic32mx5xx/6xx/7xx ds60001156h-page 164 ? 2009-2013 microchip technology inc. register 10-8: dchxecon: dma cha nnel ?x? event control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chairq<7:0> (1) 15:8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chsirq<7:0> (1) 7:0 s-0 s-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 cforce cabort paten sirqen airqen ? ? ? legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-16 chairq<7:0>: channel transfer abort irq bits (1) 11111111 = interrupt 255 will abort any transfers in progress and set chaif flag ? ? ? 00000001 = interrupt 1 will abort any transfers in progress and set chaif flag 00000000 = interrupt 0 will abort any transfers in progress and set chaif flag bit 15-8 chsirq<7:0>: channel transfer start irq bits (1) 11111111 = interrupt 255 will initiate a dma transfer ? ? ? 00000001 = interrupt 1 will initiate a dma transfer 00000000 = interrupt 0 will initiate a dma transfer bit 7 cforce: dma forced transfer bit 1 = a dma transfer is forced to begin when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 6 cabort: dma abort transfer bit 1 = a dma transfer is aborted when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 5 paten: channel pattern match abort enable bit 1 = abort transfer and clear chen on pattern match 0 = pattern match is disabled bit 4 sirqen: channel start irq enable bit 1 = start channel cell transfer if an interrupt matching chsirq occurs 0 = interrupt number chsirq is ignor ed and does not start a transfer bit 3 airqen: channel abort irq enable bit 1 = channel transfer is aborted if an interrupt matching chairq occurs 0 = interrupt number chairq is ignor ed and does not terminate a transfer bit 2-0 unimplemented: read as ? 0 ? note 1: see table 7-1: ?interrupt irq, vector and bit location? for the list of available interrupt irq sources.
? 2009-2013 microchip technology inc. ds60001156h-page 165 pic32mx5xx/6xx/7xx register 10-9: dchxint: dma channel ?x? interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdie chshie chddie chdhie chb cie chccie chtaie cherie 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23 chsdie: channel source done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 22 chshie: channel source half empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 chddie: channel destination done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 chdhie: channel destination half full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 chbcie: channel block transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 chccie: channel cell transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 chtaie: channel transfer abort interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 cherie: channel address error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15-8 unimplemented: read as ? 0 ? bit 7 chsdif: channel source done interrupt flag bit 1 = channel source pointer has reached end of source (chsptr = chssiz) 0 = no interrupt is pending bit 6 chshif: channel source half empty interrupt flag bit 1 = channel source pointer has reached mi dpoint of source (chsptr = chssiz/2) 0 = no interrupt is pending
pic32mx5xx/6xx/7xx ds60001156h-page 166 ? 2009-2013 microchip technology inc. bit 5 chddif: channel destination done interrupt flag bit 1 = channel destination pointer has reached end of destination (chdptr = chdsiz) 0 = no interrupt is pending bit 4 chdhif: channel destination half full interrupt flag bit 1 = channel destination pointer has reached midpoint of destination (chdptr = chdsiz/2) 0 = no interrupt is pending bit 3 chbcif: channel block transfer complete interrupt flag bit 1 = a block transfer has been completed (the larger of chssiz/chdsiz bytes has been transferred), or a pattern match event occurs 0 = no interrupt is pending bit 2 chccif: channel cell transfer complete interrupt flag bit 1 = a cell transfer has been completed (chcsiz bytes have been transferred) 0 = no interrupt is pending bit 1 chtaif: channel transfer abort interrupt flag bit 1 = an interrupt matching chairq has been det ected and the dma transfer has been aborted 0 = no interrupt is pending bit 0 cherif: channel address error interrupt flag bit 1 = a channel address error has been detected (either the source or the destination address is invalid) 0 = no interrupt is pending register 10-9: dchxint: dma channel ?x? in terrupt control register (continued)
? 2009-2013 microchip technology inc. ds60001156h-page 167 pic32mx5xx/6xx/7xx register 10-10: dchxssa: dma channel ?x? source start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chssa<31:0> channel source start address bits channel source start address. note: this must be the physical address of the source. register 10-11: dchxdsa: dma channel ?x? destination start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chdsa<31:0>: channel destination start address bits channel destination start address. note: this must be the physical address of the destination.
pic32mx5xx/6xx/7xx ds60001156h-page 168 ? 2009-2013 microchip technology inc. register 10-12: dchxssiz: dma channel ?x? source size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chssiz<15:0>: channel source size bits 1111111111111111 = 65,535 byte source size ? ? ? 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size register 10-13: dchxdsiz: dma chann el ?x? destination size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdsiz<15:0>: channel destination size bits 1111111111111111 = 65,535 byte destination size ? ? ? 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size
? 2009-2013 microchip technology inc. ds60001156h-page 169 pic32mx5xx/6xx/7xx register 10-14: dchxsptr: dma channel ?x? source pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chsptr<15:0>: channel source pointer bits 1111111111111111 = points to byte 65,535 of the source ? ? ? 0000000000000001 = points to byte 1 of the source 0000000000000000 = points to byte 0 of the source note: when in pattern detect mode, this regi ster is reset on a pattern detect. register 10-15: dchxdptr: dma channe l ?x? destination pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdptr<15:0>: channel destination pointer bits 1111111111111111 = points to byte 65,535 of the destination ? ? ? 0000000000000001 = points to byte 1 of the destination 0000000000000000 = points to byte 0 of the destination
pic32mx5xx/6xx/7xx ds60001156h-page 170 ? 2009-2013 microchip technology inc. register 10-16: dchxcsiz: dma channel ?x? cell-size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcsiz<15:0>: channel cell-size bits 1111111111111111 = 65,535 bytes transferred on an event ? ? ? 0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event register 10-17: dchxcptr: dma channel ?x? cell pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcptr<7:0>: channel cell progress pointer bits 1111111111111111 = 65,535 bytes have been tran sferred since the last event ? ? ? 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event note: when in pattern detect mode, this register is reset on a pattern detect.
? 2009-2013 microchip technology inc. ds60001156h-page 171 pic32mx5xx/6xx/7xx register 10-18: dchxdat: dma channel ?x? pattern data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpdat<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 chpdat<7:0>: channel data register bits pattern terminate mode: data to be matched must be stored in this register to allow terminate on match. all other modes: unused.
pic32mx5xx/6xx/7xx ds60001156h-page 172 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 173 pic32mx5xx/6xx/7xx 11.0 usb on-the-go (otg) the universal serial bus (usb) module contains analog and digital components to provide a usb 2.0 full-speed and low-speed embedded host, full-speed device or otg implementation with a minimum of external components. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), a dedicated usb dma control- ler, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32 usb otg module is presented in figure 11-1 . the clock generator provides the 48 mhz clock required for usb full-speed and low-speed communi- cation. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides t he analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. the usb dma controller transfers data between the data buffers in ram and the sie. the inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. the usb module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb otg support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? transaction handshaking performed by hardware ? endpoint buffering anywhere in system ram ? integrated dma to acce ss system ram and flash note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 27. ?usb on- the-go (otg)? (ds60001126) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the implementation and use of the usb specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigating and satisfying any applicable licensing obligations.
pic32mx5xx/6xx/7xx ds60001156h-page 174 ? 2009-2013 microchip technology inc. figure 11-1: pic32mx5xx/6xx/7xx family usb interface diagram osc1 osc2 primary oscillator 8 mhz typical frc oscillator tun<5:0> (4) pll 48 mhz usb clock (7) div x upllen (6) (pb out) (1) ufrcen (3) (p osc ) upllidiv (6) uf in (5) div 2 v usb 3 v 3 d+ (2) d- (2) id (8) bus transceiver sie v buson (8) comparators usb srp charge srp discharge registers and control interface transceiver power 3.3v to clock generator for core and peripherals sleep or idle sleep usben usb suspend cpu clock not p osc usb module voltage system ram usb suspend full-speed pull-up host pull-down low-speed pull-up host pull-down id pull-up dma note 1: pb clock is only available on th is pin for select ec modes. 2: pins can be used as digital inputs when usb is not enabled. 3: this bit field is contai ned in the osccon register. 4: this bit field is contained in the osctrm register. 5: usb pll u f in requirements: 4 mhz. 6: this bit field is contained in the devcfg2 register. 7: a 48 mhz clock is required for proper usb operation. 8: pins can be used as gpio wh en the usb module is disabled.
? 2009-2013 microchip technology inc. ds60001156h-page 175 pic32mx5xx/6xx/7xx 11.1 control registers register 11-1: u1otgir: usb otg interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs u-0 r/wc-0, hs idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idif: id state change indicator bit 1 = change in id state detected 0 = no change in id state detected bit 6 t1msecif: 1 millisecond timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit 1 = usb line state has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit 1 = activity on the d+, d-, id or v bus pins has caused the device to wake-up 0 = activity has not been detected bit 3 sesvdif: session valid change indicator bit 1 =v bus voltage has dropped below the session end level 0 =v bus voltage has not dropped below the session end level bit 2 sesendif: b-device v bus change indicator bit 1 = a change on the session end input was detected 0 = no change on the session end input was detected bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdif: a-device v bus change indicator bit 1 = change on the session valid input detected 0 = no change on the session valid input detected
pic32mx5xx/6xx/7xx ds60001156h-page 176 ? 2009-2013 microchip technology inc. register 11-2: u1otgie: usb otg interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idie: id interrupt enable bit 1 = id interrupt enabled 0 = id interrupt disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 lstateie: line state interrupt enable bit 1 = line state interrupt enabled 0 = line state interrupt disabled bit 4 actvie: bus activity interrupt enable bit 1 = activity interrupt enabled 0 = activity interrupt disabled bit 3 sesvdie: session valid interrupt enable bit 1 = session valid interrupt enabled 0 = session valid interrupt disabled bit 2 sesendie: b-session end interrupt enable bit 1 = b-session end interrupt enabled 0 = b-session end interrupt disabled bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdie: a-v bus valid interrupt enable bit 1 =a-v bus valid interrupt enabled 0 =a-v bus valid interrupt disabled
? 2009-2013 microchip technology inc. ds60001156h-page 177 pic32mx5xx/6xx/7xx register 11-3: u1otgstat: usb otg status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 r-0 u-0 r-0 r-0 u-0 r-0 id ?lstate ? sesvd sesend ? vbusvd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 id: id pin state indicator bit 1 = no cable is attached or a ?type b? cabl e has been inserted into the usb receptacle 0 = a ?type a? otg cable has been inserted into the usb receptacle bit 6 unimplemented: read as ? 0 ? bit 5 lstate: line state stable indicator bit 1 = usb line state (se0 (u1con<6> and jstate (u1con<7>) has been stable for the previous 1 ms 0 = usb line state (se0 (u1con<6> and jstate (u1con<7>) has not been stable for the previous 1 ms bit 4 unimplemented: read as ? 0 ? bit 3 sesvd: session valid indicator bit 1 =v bus voltage is above session valid on the a or b device 0 =v bus voltage is below session valid on the a or b device bit 2 sesend: b-device session end indicator bit 1 =v bus voltage is below session valid on the b device 0 =v bus voltage is above session valid on the b device bit 1 unimplemented: read as ? 0 ? bit 0 vbusvd: a-device v bus valid indicator bit 1 =v bus voltage is above session valid on the a device 0 =v bus voltage is below session valid on the a device
pic32mx5xx/6xx/7xx ds60001156h-page 178 ? 2009-2013 microchip technology inc. register 11-4: u1otgcon: usb otg control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor is enabled 0 = d+ data line pull-up resistor is disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor is enabled 0 = d- data line pull-up resistor is disabled bit 5 dppuldwn: d+ pull-down enable bit 1 = d+ data line pull-down resistor is enabled 0 = d+ data line pull-down resistor is disabled bit 4 dmpuldwn: d- pull-down enable bit 1 = d- data line pull-down resistor is enabled 0 = d- data line pull-down resistor is disabled bit 3 vbuson: v bus power-on bit 1 =v bus line is powered 0 =v bus line is not powered bit 2 otgen: otg functionality enable bit 1 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under software control 0 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under usb hardware control bit 1 vbuschg: v bus charge enable bit 1 =v bus line is charged through a pull-up resistor 0 =v bus line is not charged through a resistor bit 0 vbusdis: v bus discharge enable bit 1 =v bus line is discharged through a pull-down resistor 0 =v bus line is not discharged through a resistor
? 2009-2013 microchip technology inc. ds60001156h-page 179 pic32mx5xx/6xx/7xx register 11-5: u1pwrc: usb power control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uactpnd ? ? uslpgrd usbbusy ? ususpend usbpwr legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uactpnd: usb activity pending bit 1 = usb bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = an interrupt is not pending bit 6-5 unimplemented: read as ? 0 ? bit 4 uslpgrd: usb sleep entry guard bit 1 = sleep entry is blocked if usb bus activity is detected or if a notification is pending 0 = usb module does not block sleep entry bit 3 usbbusy: usb module busy bit 1 = usb module is active or disabled, but not ready to be enabled 0 = usb module is not active and is ready to be enabled note: when usbpwr = 0 and usbbusy = 1 , status from all other registers is invalid and writes to all usb module registers produce undefined results. bit 2 unimplemented: read as ? 0 ? bit 1 ususpend: usb suspend mode bit 1 = usb module is placed in suspend mode (the 48 mhz usb clock will be gated off. the tr ansceiver is placed in a low-power state.) 0 = usb module operates normally bit 0 usbpwr: usb operation enable bit 1 = usb module is turned on 0 = usb module is disabled (outputs held inactive, device pins not used by usb, analog features are shut down to reduce power consumption.)
pic32mx5xx/6xx/7xx ds60001156h-page 180 ? 2009-2013 microchip technology inc. register 11-6: u1ir: usb interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r-0 r/wc-0, hs stallif attachif (1) resumeif (2) idleif trnif (3) sofif uerrif (4) urstif (5) detachif (6) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = in host mode a stall handshake was received du ring the handshake phase of the transaction. in device mode, a stall handshake was transmitted during the handshake phase of the transaction. 0 = stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit (1) 1 = peripheral attachment wa s detected by the usb module 0 = peripheral attachment was not detected bit 5 resumeif: resume interrupt bit (2) 1 = k-state is observed on the d+ or d- pin for 2.5 s 0 = k-state is not observed bit 4 idleif: idle detect interrupt bit 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing complete interrupt bit (3) 1 = processing of current token is complete; a read of the u1stat register will provide endpoint information 0 = processing of current token not complete bit 2 sofif: sof token interrupt bit 1 = sof token received by the peripheral or the sof threshold reached by the host 0 = sof token was not received nor threshold reached bit 1 uerrif : usb error condition interrupt bit (4) 1 = unmasked error condition has occurred 0 = unmasked error cond ition has not occurred bit 0 urstif: usb reset interrupt bit (device mode) (5) 1 = valid usb reset has occurred 0 = no usb reset has occurred detachif: usb detach interrupt bit (host mode) (6) 1 = peripheral detachment was detected by the usb module 0 = peripheral detachment was not detected note 1: this bit is only valid if the hosten bit is set (see register 11-11 ), there is no activity on the usb for 2.5 s, and the current bus state is not se0. 2: when not in suspend mode, this interrupt should be disabled. 3: clearing this bit will cause the stat fifo to advance. 4: only error conditions enabled through the u1eie register will set this bit. 5: device mode. 6: host mode.
? 2009-2013 microchip technology inc. ds60001156h-page 181 pic32mx5xx/6xx/7xx register 11-7: u1ie: usb interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie resumeie idleie trnie sofie uerrie (1) urstie (2) detachie (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = stall interrupt enabled 0 = stall interrupt disabled bit 6 attachie: attach interrupt enable bit 1 = attach interrupt enabled 0 = attach interrupt disabled bit 5 resumeie: resume interrupt enable bit 1 = resume interrupt enabled 0 = resume interrupt disabled bit 4 idleie: idle detect interrupt enable bit 1 = idle interrupt enabled 0 = idle interrupt disabled bit 3 trnie: token processing complete interrupt enable bit 1 = trnif interrupt enabled 0 = trnif interrupt disabled bit 2 sofie: sof token interrupt enable bit 1 = sofif interrupt enabled 0 = sofif interrupt disabled bit 1 uerrie: usb error interrupt enable bit (1) 1 = usb error interrupt enabled 0 = usb error interrupt disabled bit 0 urstie: usb reset interrupt enable bit (2) 1 = urstif interrupt enabled 0 = urstif interrupt disabled detachie: usb detach interrupt enable bit (3) 1 = dattchif interrupt enabled 0 = dattchif interrupt disabled note 1: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set. 2: device mode. 3: host mode.
pic32mx5xx/6xx/7xx ds60001156h-page 182 ? 2009-2013 microchip technology inc. register 11-8: u1eir: usb error interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs btsef bmxef dmaef (1) btoef (2) dfn8ef crc16ef crc5ef (4) pidef eofef (3,5) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = packet rejected due to bit stuff error 0 = packet accepted bit 6 bmxef: bus matrix error flag bit 1 = invalid base address of the bdt, or the address of an individual buffer pointed to by a bdt entry 0 = no address error bit 5 dmaef: dma error flag bit (1) 1 = usb dma error condition detected 0 =no dma error bit 4 btoef: bus turnaround time-out error flag bit (2) 1 = bus turnaround time-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field received is not an integral number of bytes 0 = data field received is an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = data packet rejected due to crc16 error 0 = data packet accepted bit 1 crc5ef: crc5 host error flag bit (4) 1 = token packet rejected due to crc5 error 0 = token packet accepted eofef: eof error flag bit (3,5) 1 = eof error condition detected 0 = no eof error condition bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed note 1: this type of error occurs when the module?s request fo r the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the receiv ed data packet causing it to be truncated. 2: this type of error occurs when more than 16-bit-tim es of idle from the previous end-of-packet (eop) has elapsed. 3: this type of error occurs when the module is tran smitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode.
? 2009-2013 microchip technology inc. ds60001156h-page 183 pic32mx5xx/6xx/7xx register 11-9: u1eie: usb error interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee (1) pidee eofee (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = btsef interrupt enabled 0 = btsef interrupt disabled bit 6 bmxee: bus matrix error interrupt enable bit 1 = bmxef interrupt enabled 0 = bmxef interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = dmaef interrupt enabled 0 = dmaef interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = btoef interrupt enabled 0 = btoef interrupt disabled bit 3 dfn8ee: data field size erro r interrupt enable bit 1 = dfn8ef interrupt enabled 0 = dfn8ef interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = crc16ef interrupt enabled 0 = crc16ef interrupt disabled bit 1 crc5ee: crc5 host error interrupt enable bit (1) 1 = crc5ef interrupt enabled 0 = crc5ef interrupt disabled eofee: eof error interrupt enable bit (2) 1 = eof interrupt enabled 0 = eof interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = pidef interrupt enabled 0 = pidef interrupt disabled note 1: device mode. 2: host mode. note: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set.
pic32mx5xx/6xx/7xx ds60001156h-page 184 ? 2009-2013 microchip technology inc. register 11-10: u1stat: usb status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 23:16 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 15:8 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r-x r-x r-x r-x u-0 u-0 endpt<3:0> dir ppbi ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 endpt<3:0>: encoded number of last endpoint activity bits (represents the number of the bdt, updated by the last usb transfer.) 1111 = endpoint 15 1110 = endpoint 14 ? ? ? 0001 =endpoint 1 0000 =endpoint 0 bit 3 dir: last buffer descriptor direction indicator bit 1 = last transaction was a transmit transfer (tx) 0 = last transaction was a receive transfer (rx) bit 2 ppbi: ping-pong buffer descriptor pointer indicator bit 1 = the last transaction was to the odd buffer descriptor bank 0 = the last transaction was to the even buffer descriptor bank bit 1-0 unimplemented: read as ? 0 ? note: the u1stat register is a window into a 4-byte fifo maintained by the usb module. u1stat value is only valid when u1ir is active. clearing the u1ir bit advances the fifo. data in register is invalid when u1ir = 0 .
? 2009-2013 microchip technology inc. ds60001156h-page 185 pic32mx5xx/6xx/7xx register 11-11: u1con: usb control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 pktdis (4) usbrst hosten (2) resume (3) ppbrst usben (4) tokbusy (1,5) sofen (5) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 jstate: live differential receiver jstate flag bit 1 = jstate was detected on the usb 0 = jstate was not detected bit 6 se0: live single-ended zero flag bit 1 = single-ended zero was detected on the usb 0 = single-ended zero was not detected bit 5 pktdis: packet transfer disable bit (4) 1 = token and packet processing disabled (set upon setup token received) 0 = token and packet processing enabled tokbusy: token busy indicator bit (1,5) 1 = token being executed by the usb module 0 = no token being executed bit 4 usbrst: module reset bit (5) 1 = usb reset generated 0 = usb reset terminated bit 3 hosten: host mode enable bit (2) 1 = usb host capability enabled 0 = usb host capability disabled bit 2 resume: resume signaling enable bit (3) 1 = resume signaling activated 0 = resume signaling disabled note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 11-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set resume for 10 ms in device mode, or for 25 ms in host mode, and then clear it to enable remote wake-up. in host mode, the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode.
pic32mx5xx/6xx/7xx ds60001156h-page 186 ? 2009-2013 microchip technology inc. bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all even/odd buffer pointers to the even buffer descriptor banks 0 = even/odd buffer pointers are not reset bit 0 usben: usb module enable bit (4) 1 = usb module and supporting circuitry enabled 0 = usb module and supporting circuitry disabled sofen: sof enable bit (5) 1 = sof token sent every 1 ms 0 = sof token disabled register 11-11: u1con: usb control register (continued) note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 11-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set resume for 10 ms in device mode, or for 25 ms in host mode, and then clear it to enable remote wake-up. in host mode, the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode.
? 2009-2013 microchip technology inc. ds60001156h-page 187 pic32mx5xx/6xx/7xx register 11-12: u1addr: usb address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden devaddr<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspden: low-speed enable indicator bit 1 = next token command to be executed at low-speed 0 = next token command to be executed at full-speed bit 6-0 devaddr<6:0>: 7-bit usb device address bits register 11-13: u1frml: usb frame number low register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 frml<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 frml<7:0>: 11-bit frame number lower bits the register bits are updated with the current fr ame number whenever a sof token is received.
pic32mx5xx/6xx/7xx ds60001156h-page 188 ? 2009-2013 microchip technology inc. register 11-14: u1frmh: usb frame number high register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? frmh<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as ? 0 ? bit 2-0 frmh<2:0>: upper 3 bits of the frame numbers bits these register bits are updated with the current frame number w henever a sof token is received. register 11-15: u1tok: usb token register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid<3:0> ep<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 pid<3:0>: token type indicator bits (1) 1101 = setup (tx) token type transaction 1001 = in (rx) token type transaction 0001 = out (tx) token type transaction note: all other values not listed, are reserved and must not be used. bit 3-0 ep<3:0>: token command endpoint address bits the four bit value must specify a valid endpoint.
? 2009-2013 microchip technology inc. ds60001156h-page 189 pic32mx5xx/6xx/7xx register 11-16: u1sof: usb sof threshold register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 cnt<7:0>: sof threshold value bits typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet register 11-17: u1bdtp1: usb buffer descriptor table page 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bdtptrl<15:9> ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-1 bdtptrl<15:9>: bdt base address bits this 7-bit value provides address bits 15 through 9 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. bit 0 unimplemented: read as ? 0 ?
pic32mx5xx/6xx/7xx ds60001156h-page 190 ? 2009-2013 microchip technology inc. register 11-18: u1bdtp2: usb buffer descriptor table page 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptrh<23:16> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptrh<23:16>: bdt base address bits this 8-bit value provides address bits 23 through 16 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. register 11-19: u1bdtp3: usb buffer descriptor table page 3 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptru<31:24> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptru<31:24>: bdt base address bits this 8-bit value provides address bits 31 through 24 of the bdt base address, defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned.
? 2009-2013 microchip technology inc. ds60001156h-page 191 pic32mx5xx/6xx/7xx register 11-20: u1cnfg1: us b configuration 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 uteye uoemon ? usbsidl ? ? ? uasuspnd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uteye: usb eye-pattern test enable bit 1 = eye-pattern test enabled 0 = eye-pattern test disabled bit 6 uoemon: usb oe monitor enable bit 1 =oe signal active; it indicates intervals during which the d+/d- lines are driving 0 =oe signal inactive bit 5 unimplemented: read as ? 0 ? bit 4 usbsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 3-1 unimplemented: read as ? 0 ? bit 0 uasuspnd: automatic suspend enable bit 1 = usb module automatically suspends upon entry to sleep mode. see the ususpend bit (u1pwrc<1>) in register 11-5 . 0 = usb module does not automatically suspend upon entry to sleep mode. software must use the ususpend bit (u1pwrc<1>) to suspend the module, including the usb 48 mhz clock.
pic32mx5xx/6xx/7xx ds60001156h-page 192 ? 2009-2013 microchip technology inc. register 11-21: u1ep0-u1ep15: usb endpoint control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd retrydis ? epcondis eprxen eptxen epstall ephshk legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspd: low-speed direct connection enable bit (host mode and u1ep0 only) 1 = direct connection to a low-speed device enabled 0 = direct connection to a low-speed device disabled; hub required with pre_pid bit 6 retrydis: retry disable bit (host mode and u1ep0 only) 1 = retry nack?d transactions disabled 0 = retry nack?d transactions enabled; retry done in hardware bit 5 unimplemented: read as ? 0 ? bit 4 epcondis: bidirectional endpoint control bit if eptxen = 1 and eprxen = 1 : 1 = disable endpoint ?n? from control transf ers; only tx and rx transfers are allowed 0 = enable endpoint ?n? for control (setup) tran sfers; tx and rx tran sfers are also allowed otherwise, this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint ?n? receive enabled 0 = endpoint ?n? receive disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint ?n? transmit enabled 0 = endpoint ?n? transmit disabled bit 1 epstall: endpoint stall status bit 1 = endpoint ?n? was stalled 0 = endpoint ?n? was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints)
? 2009-2013 microchip technology inc. ds60001156h-page 193 pic32mx5xx/6xx/7xx 12.0 i/o ports general purpose i/o pins ar e the simplest of peripher- als. they allow the pic32 mcu to monitor and control other devices. to add flexib ility and functionality, some pins are multiplexed with alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. following are some of the key features of this module: ? individual output pin open-drain enable/disable ? individual input pin weak pull-up enable/disable ? monitor selective inputs and generate interrupt when change in pin state is detected ? operation during sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 12-1 illustrates a block diagram of a typical multiplexed i/o port. figure 12-1: block diagram of a typical multiplexed port structure note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?i/o ports? (ds60001120) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris 0 1 rd odc sysclk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 sysclk wr odc odc tris lat sleep 1 0 1 0 output multiplexers i/o cell synchronization r peripheral input legend: r = peripheral input buffer types may vary. refer to ta b l e 1 - 1 for peripheral details. note: this block diagram is a general representation of a shared port/p eripheral structure is only for illustration purposes. the act ual structure for any specific port/peripheral combination may be different than it is shown here. peripheral input buffer
pic32mx5xx/6xx/7xx ds60001156h-page 194 ? 2009-2013 microchip technology inc. 12.1 parallel i/o (pio) ports all port pins have three registers (tris, lat and port) that are directly associated with their operation. tris is a data direction or tri-state control register that determines whether a digital pin is an input or an output. setting a trisx register bit = 1 , configures the corresponding i/o pin as an input; setting a trisx register bit = 0 , configures the corresponding i/o pin as an output. all port i/o pins are defined as inputs after a device reset. certain i/o pins are shared with analog peripherals and default to analog inputs after a device reset. port is a register used to read the current state of the signal applied to the port i/o pins. writing to a portx register performs a write to the port?s latch, latx register, latching the data to the port?s i/o pins. lat is a register used to write data to the port i/o pins. the latx latch register holds the data written to either the latx or portx registers. reading the latx latch register reads the last value written to the corresponding port or latch register. not all port i/o pins are implemented on some devices, therefore, the corresponding portx, latx and trisx register bits will read as zeros. 12.1.1 clr, set and inv registers every i/o module register has a corresponding clear (clr), set (set) and invert (inv) register designed to provide fast atomic bit manipulations. as the name of the register implies, a value written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ? 1 ? are modified. bits specified as ? 0 ? are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. 12.1.2 digital inputs pins are configured as digital inputs by setting the corresponding tris register bits = 1 . when configured as inputs, they are either ttl buffers or schmitt triggers. several digital pins share functionality with analog inputs and default to the analog inputs at por. setting the corresponding bit in the ad1pcfg register = 1 enables the pin as a digital pin. the maximum input voltage allowed on the input pins is the same as the maximum v ih specification. refer to section 31.0 ?electri cal characteristics? for v ih specification details. 12.1.3 analog inputs certain pins can be configured as analog inputs used by the adc and comparator modules. setting the corresponding bits in the ad1pcfg register = 0 enables the pin as an analog input pin and must have the corresponding tris bit set = 1 (input). if the tris bit is cleared = 0 (output), the digital output level (v oh or v ol ) will be converted. any time a port i/o pin is configured as analog, its digital input is disabled and the corresponding portx register bit will read ? 0 ?. the ad1pcfg register has a default value of 0x0000; therefore, all pins that sh are anx functions are analog (not digital) by default. 12.1.4 digital outputs pins are configured as digital outputs by setting the corresponding tris register bits = 0 . when configured as digital outputs, these pins are cmos drivers or can be configured as open-drain outputs by setting the corresponding bits in the open-drain configuration (odcx) register. the open-drain feature allows generation of outputs higher than v dd (e.g., 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see the ? pin diagrams ? section for the available pins and their functionality. 12.1.5 analog outputs certain pins can be configured as analog outputs, such as the cv ref output voltage used by the comparator module. configuring the comparator reference module to provide this output will present the analog output voltage on the pin, independ ent of the tris register setting for the corresponding pin. 12.1.6 input change notification the input change notification function of the i/o ports (cnx) allows devices to gen erate interrupt requests in response to change-of-state on selected pin. each cnx pin also has a weak pull-up, which acts as a current source connected to the pin. the pull-ups are enabled by setting the corresponding bit in the cnpue register. note: using a portxinv register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions, as compared to the traditional read-modify-write method, as follows: portc ^ = 0x0001 ; note: analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications.
? 2009-2013 microchip technology inc. ds60001156h-page 195 pic32mx5xx/6xx/7xx 12.2 control register register 12-1: cncon: chang e notice control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: change notice (cn) control on bit 1 = cn is enabled 0 = cn is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = idle mode halts cn operation 0 = idle mode does not affect cn operation bit 12-0 unimplemented: read as ? 0 ?
pic32mx5xx/6xx/7xx ds60001156h-page 196 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 197 pic32mx5xx/6xx/7xx 13.0 timer1 this family of pic32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a free-run- ning interval timer for various timing applications and counting external events. this timer can also be used with the low-power secondary oscillator (s osc ) for real-time clock (rtc) applications. the following modes are supported: ? synchronous internal timer ? synchronous internal gated timer ? synchronous external timer ? asynchronous external timer 13.1 additional supported features ? selectable clock prescaler ? timer operation during idle and sleep mode ? fast bit manipulation using clr, set and inv registers ? asynchronous mode can be used with the s osc to function as a real-time clock (rtc) a simplified block diagram of the timer1 module is illustrated in figure 13-1 . figure 13-1: timer1 block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds60001105) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. on (t1con<15>) sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen (1) event flag 1 0 tsync (t1con<2>) tgate (t1con<7>) tgate (t1con<7>) pbclk 1 0 tcs (t1con<1>) gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q qd (t1con<5:4>) note 1: the default state of the soscen (osccon<1>) during a device reset is controll ed by the fsoscen bit in configuration word, devcfg1.
pic32mx5xx/6xx/7xx ds60001156h-page 198 ? 2009-2013 microchip technology inc. 13.2 control register register 13-1: t1con: type a timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r-0 u-0 u-0 u-0 on (1) ? sidl twdis twip ? ? ? 7:0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate ? tckps<1:0> ? tsync tcs ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1) 1 = timer is enabled 0 = timer is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation when device is in idle mode bit 12 twdis: asynchronous timer write disable bit 1 = writes to tmr1 are ignored until pending write operation completes 0 = back-to-back writes are enabled (legacy asynchronous timer functionality) bit 11 twip: asynchronous timer write in progress bit in asynchronous timer mode: 1 = asynchronous write to tmr1 register in progress 0 = asynchronous write to tmr1 register complete in synchronous timer mode: this bit is read as ? 0 ?. bit 10-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6 unimplemented: read as ? 0 ? note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2009-2013 microchip technology inc. ds60001156h-page 199 pic32mx5xx/6xx/7xx bit 5-4 tckps<1:0>: timer input clock pr escale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer external clock input synchronization selection bit when tcs = 1 : 1 = external clock input is synchronized 0 = external clock input is not synchronized when tcs = 0 : this bit is ignored. bit 1 tcs: timer clock source select bit 1 = external clock from txcki pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 13-1: t1con: type a time r control register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx5xx/6xx/7xx ds60001156h-page 200 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 201 pic32mx5xx/6xx/7xx 14.0 timer2/3, timer4/5 this family of pic32 devices features four synchronous 16-bit timers (default) that can operate as a free- running interval timer for various timing applications and counting external events. the following modes are supported: ? synchronous internal 16-bit timer ? synchronous internal 16-bit gated timer ? synchronous external 16-bit timer two 32-bit synchronous timers are available by combining timer2 with timer3 and timer4 with timer5. the 32-bit timers can operate in three modes: ? synchronous internal 32-bit timer ? synchronous internal 32-bit gated timer ? synchronous external 32-bit timer 14.1 additional supported features ? selectable clock prescaler ? timers operational during cpu idle ? time base for input capture and output compare modules (only timer2 and timer3) ? adc event trigger (only timer3) ? fast bit manipulation using clr, set and inv registers figure 14-1: timer2/3 and time r4/5 block diagram (16-bit) note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds60001105) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: in this chapter, references to registers, txcon, tmrx and prx, use ?x? to represent timer2 through timer5 in 16-bit modes. in 32-bit modes, ?x? represents timer2 or timer4; ?y? represents timer3 or timer5. sync prx txif equal comparator x 16 tmrx reset event flag q q d tgate (txcon<7>) 1 0 gate txck (2) sync on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk trigger (1) adc event note 1: adc event trigger is only available on timer3. 2: txck pins are not avai lable on 64-pin devices.
pic32mx5xx/6xx/7xx ds60001156h-page 202 ? 2009-2013 microchip technology inc. figure 14-2: timer2/3 and time r4/5 block diagram (32-bit) tmry tmrx tyif event equal 32-bit comparator pry prx reset ls half word ms half word flag note 1: in this diagram, the use of ?x? in regi sters, txcon, tmrx, prx and txck, refers to either timer2 or timer4; the use of ?y? in registers, tycon, tmry, pry, ty if, refers to either timer3 or timer5. 2: txck pins are not avai lable on 64-pin devices. 3: adc event trigger is only avai lable on the timer2/3 pair. tgate (txcon<7>) 0 1 pbclk gate txck (2) sync sync adc event trigger (3) on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q qd x 1
? 2009-2013 microchip technology inc. ds60001156h-page 203 pic32mx5xx/6xx/7xx 14.2 control register register 14-1: txcon: type b timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1,3) ?sidl (4) ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate (3) tckps<2:0> (3) t32 (2) ?tcs (3) ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1,3) 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit (4) 1 = discontinue operation when device enters idle mode 0 = continue operation when device is in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit (3) when tcs = 1 : this bit is ignored and is read as ? 0 ?. when tcs = 0 : 1 = gated time accumu lation is enabled 0 = gated time accumu lation is disabled bit 6-4 tckps<2:0>: timer input clock prescale select bits (3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is only available on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no ef fect for odd numbered timers (timer1, timer3, and tim- er5). all timer functions are set through the even numbered timers. 4: while operating in 32-bit mode, this bit must be clea red on odd numbered timers to enable the 32-bit timer in idle mode.
pic32mx5xx/6xx/7xx ds60001156h-page 204 ? 2009-2013 microchip technology inc. bit 3 t32: 32-bit timer mode select bit (2) 1 = odd numbered and even numbered timers form a 32-bit timer 0 = odd numbered and even numbered timers form a separate 16-bit timer bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer clock source select bit (3) 1 = external clock from txck pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 14-1: txcon: type b timer control register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is only available on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no ef fect for odd numbered timers (timer1, timer3, and tim- er5). all timer functions are set through the even numbered timers. 4: while operating in 32-bit mode, this bit must be cl eared on odd numbered timers to enable the 32-bit timer in idle mode.
? 2009-2013 microchip technology inc. ds60001156h-page 205 pic32mx5xx/6xx/7xx 15.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the input capture module capt ures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. the following events cause capture events: ? simple capture event modes: - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin ? capture timer value on every edge (rising and falling) ? capture timer value on every edge (rising and falling), specified edge first. ? prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of two 16-bit timers (timer2 or timer3) for the time base, or two 16-bit timers (timer2 and timer3) together to form a 32-bit timer. the se lected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? input capture module can also be used to provide additional sources of external interrupts figure 15-1: input capture block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?input capture? (ds60001122) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. prescaler 1, 4, 16 edge detect fifo control interrupt event generation icxbuf<31:16> interrupt timer3 timer2 icxcon ici<1:0> icx input 0 1 icxbuf<15:0> data space interface peripheral data bus c32 ictmr icm<2:0> fedge icbne icov icm<2:0>
pic32mx5xx/6xx/7xx ds60001156h-page 206 ? 2009-2013 microchip technology inc. 15.1 control register register 15-1: ic x con: input capture ? x ? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on (1) ?sidl ? ? ?fedgec32 7:0 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: input capture module enable bit (1) 1 = module enabled 0 = disable and reset module, disable clocks, disable interrupt generation and allow sfr modifications bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = halt in idle mode 0 = continue to operate in idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9 fedge: first capture edge select bit (only used in mode 6, icm<2:0> = 110 ) 1 = capture rising edge first 0 = capture falling edge first bit 8 c32: 32-bit capture select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ictmr: timer select bit (does not affect timer selection when c32 (icxcon<8>) is ? 1 ?) 1 = timer2 is the counter source for capture 0 = timer3 is the counter source for capture bit 6-5 ici<1:0>: interrupt control bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty; at least one more capture value can be read 0 = input capture buffer is empty note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2009-2013 microchip technology inc. ds60001156h-page 207 pic32mx5xx/6xx/7xx bit 2-0 icm<2:0>: input capture mode select bits 111 = interrupt-only mode (only supported while in sleep mode or idle mode) 110 = simple capture event mode ? every edge, sp ecified edge first and every edge thereafter 101 = prescaled capture event mode ? every sixteenth rising edge 100 = prescaled capture event mode ? every fourth rising edge 011 = simple capture event mode ? every rising edge 010 = simple capture event mode ? every falling edge 001 = edge detect mode ? every edge (rising and falling) 000 = input capture module is disabled register 15-1: ic x con: input capture ? x ? control register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx5xx/6xx/7xx ds60001156h-page 208 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 209 pic32mx5xx/6xx/7xx 16.0 output compare the output compare module is used to generate a single pulse or a series of pulses in response to selected time base events. for all modes of operation, the output compare module compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the output compare module generates an event based on the selected mode of operation. some of the key features of the output compare module are: ? multiple output compare modules in a device ? programmable interrupt generation on compare event ? single and dual compare modes ? single and continuous output pulse generation ? pulse-width modulation (pwm) mode ? hardware-based pwm fault detection and automatic output disable ? programmable selection of 16-bit or 32-bit time bases ? can operate from either of two available 16-bit time bases or a single 32-bit time base figure 16-1: output compare module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?output compare? (ds6000 1111) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the register s associated with the respec tive output compare channels, 1 through 5. 2: the ocfa pin controls the oc1-oc4 channels. the ocfb pin controls the oc5 channel. 3: each output compare channel can use one of two selectabl e 16-bit time bases or a single 32-bit timer base. 0 1 octsel 0 1 16 16 ocfa or ocfb (2) tmr register inputs from time bases (3) period match signals from time bases (3) logic output enable
pic32mx5xx/6xx/7xx ds60001156h-page 210 ? 2009-2013 microchip technology inc. 16.1 control register register 16-1: ocxcon: output compare ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1) ?sidl ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? oc32 ocflt (2) octsel ocm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: output compare module on bit (1) 1 = output compare module is enabled 0 = output compare module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters idle mode 0 = continue operation when cpu is in idle mode bit 12-6 unimplemented: read as ? 0 ? bit 5 oc32: 32-bit compare mode bit 1 = ocxr<31:0> and/or ocxrs<31:0> are used fo r comparisions to the 32-bit timer source 0 = ocxr<15:0> and ocxrs<15:0> are used for comparisons to the 16-bit timer source bit 4 ocflt: pwm fault condition status bit (2) 1 = pwm fault condition has occurred (only cleared in hardware) 0 = pwm fault condition has not occurred bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for this output compare module 0 = timer2 is the clock source for this output compare module bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx; fault pin enabled 110 = pwm mode on ocx; fault pin disabled 101 = initialize ocx pin low; generate continuous output pulses on ocx pin 100 = initialize ocx pin low; generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high; compare event forces ocx pin low 001 = initialize ocx pin low; compare event forces ocx pin high 000 = output compare peripheral is dis abled but continues to draw current note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is only used when ocm<2:0> = 111 . it is read as ? 0 ? in all other modes.
? 2009-2013 microchip technology inc. ds60001156h-page 211 pic32mx5xx/6xx/7xx 17.0 serial peripheral interface (spi) the spi module is a synchronous serial interface that is useful for communicatin g with external peripherals and other microcontroller devices. these peripheral devices may be serial eeprom s, shift registers, dis- play drivers, analog-to-dig ital converters, etc. the pic32 spi module is compatible with motorola ? spi and siop interfaces. some of the key features of this module include: ? master mode and slave mode support ? four different clock formats ? enhanced framed spi protocol support ? user-configurable 8-bit, 16-bit and 32-bit data width ? separate spi fifo buffers for receive and transmit - fifo buffers act as 4/8/16-level deep fifos based on 32/16/8-bit data width ? programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer ? operation during sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 17-1: spi module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the inform ation in this data sheet, refer to section 23. ?serial peripheral interface (spi)? (ds60001106) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. internal data bus sdix sdox ssx /f sync sckx spixsr bit 0 shift control edge select enable master clock baud rate slave select sync control clock control transmit receive and frame note: access spixtxb and spixrxb fi fos via spixbuf register. fifos share address spixbuf spixbuf generator pbclk write read spixtxb fifo spixrxb fifo
pic32mx5xx/6xx/7xx ds60001156h-page 212 ? 2009-2013 microchip technology inc. 17.1 control registers register 17-1: spixcon: spi control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? spife enhbuf (2) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl dissdo mode32 mode16 smp cke (3) 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp msten ? stxisel<1:0> s rxisel<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 frmen: framed spi support bit 1 = framed spi support is enabled (ssx pin used as fsync input/output) 0 = framed spi support is disabled bit 30 frmsync: frame sync pulse direction control on ssx pin bit (only framed spi mode) 1 = frame sync pulse input (slave mode) 0 = frame sync pulse output (master mode) bit 29 frmpol: frame sync polarity bit (only framed spi mode) 1 = frame pulse is active-high 0 = frame pulse is active-low bit 28 mssen: master mode slave select enable bit 1 = slave select spi support enabled. the ss pin is automatically driven during transmission in master mode. polarity is de termined by the frmpol bit. 0 = slave select spi support is disabled. bit 27 frmsypw: frame sync pulse width bit 1 = frame sync pulse is one character wide 0 = frame sync pulse is one clock wide bit 26-24 frmcnt<2:0>: frame sync pulse counter bits. controls th e number of data characters transmitted per pulse. this bit is only valid in framed sync mode. 111 = reserved 110 = reserved 101 = generate a frame sync pulse on every 32 data characters 100 = generate a frame sync pulse on every 16 data characters 011 = generate a frame sync pulse on every 8 data characters 010 = generate a frame sync pulse on every 4 data characters 001 = generate a frame sync pulse on every 2 data characters 000 = generate a frame sync pulse on every data character bit 23-18 unimplemented: read as ? 0 ? bit 17 spife: frame sync pulse edge select bit (only framed spi mode) 1 = frame synchronization pulse coincides with the first bit clock 0 = frame synchronization pulse precedes the first bit clock note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ).
? 2009-2013 microchip technology inc. ds60001156h-page 213 pic32mx5xx/6xx/7xx bit 16 enhbuf: enhanced buffer enable bit (2) 1 = enhanced buffer mode is enabled 0 = enhanced buffer mode is disabled bit 15 on: spi peripheral on bit (1) 1 = spi peripheral is enabled 0 = spi peripheral is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module (pin is controlled by associated port register) 0 = sdox pin is controlled by the module bit 11-10 mode<32,16>: 32/16-bit communication select bits mode32 mode16 communication 1x 32-bit 01 16-bit 00 8-bit bit 9 smp: spi data input sample phase bit master mode (msten = 1 ): 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode (msten = 0 ): smp value is ignored when spi is used in slave mode. the module always uses smp = 0 . bit 8 cke: spi clock edge select bit (3) 1 = serial output data changes on transition from acti ve clock state to idle clock state (see ckp bit) 0 = serial output data changes on transition from idle clock state to active clock state (see ckp bit) bit 7 ssen: slave select enable (slave mode) bit 1 = ssx pin used for slave mode 0 = ssx pin not used for slave mode (pin is controlled by port function) bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode bit 4 unimplemented: read as ? 0 ? bit 3-2 stxisel<1:0>: spi transmit buffer empty interrupt mode bits 11 = interrupt is generated when the buffer is not full (has one or more empty elements) 10 = interrupt is generated when the buffer is empty by one-half or more 01 = interrupt is generated when the buffer is completely empty 00 = interrupt is generated when the last transfer is shifted out of spisr and transmit operations are complete bit 1-0 srxisel<1:0>: spi receive buffer full interrupt mode bits 11 = interrupt is generated when the buffer is full 10 = interrupt is generated when the buffer is full by one-half or more 01 = interrupt is generated when the buffer is not empty 00 = interrupt is generated when the last word in th e receive buffer is read (i.e., buffer is empty) register 17-1: spixcon: spi co ntrol register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ).
pic32mx5xx/6xx/7xx ds60001156h-page 214 ? 2009-2013 microchip technology inc. register 17-2: spixstat: spi status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? rxbufelm<4:0> 23:16 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? txbufelm<4:0> 15:8 u-0 u-0 u-0 u-0 r-0 u-0 u-0 r-0 ? ? ? ? spibusy ? ?spitur 7:0 r-0 r/w-0 r-0 u-0 r-1 u-0 r-0 r-0 srmt spirov spirbe ?spitbe ? spitbf spirbf legend: c = clearable bit hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-24 rxbufelm<4:0>: receive buffer element count bits (only valid when enhbuf = 1 ) bit 23-21 unimplemented: read as ? 0 ? bit 20-16 txbufelm<4:0>: transmit buffer element count bits (only valid when enhbuf = 1 ) bit 15-12 unimplemented: read as ? 0 ? bit 11 spibusy: spi activity status bit 1 = spi peripheral is currently busy with some transactions 0 = spi peripheral is currently idle bit 10-9 unimplemented: read as ? 0 ? bit 8 spitur: transmit under run bit 1 = transmit buffer has encountered an underrun condition 0 = transmit buffer has no underrun condition this bit is only valid in framed sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 srmt: shift register empty bit (only valid when enhbuf = 1 ) 1 = when spi module shift register is empty 0 = when spi module shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new data is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred this bit is set in hardware; can only be cleared (= 0 ) in software. bit 5 spirbe: rx fifo empty bit (only valid when enhbuf = 1 ) 1 = rx fifo is empty (crptr = swptr) 0 = rx fifo is not empty (crptr ? ? swptr) bit 4 unimplemented: read as ? 0 ? bit 3 spitbe: spi transmit buffer empty status bit 1 = transmit buffer, spixtxb is empty 0 = transmit buffer, spixtxb is not empty automatically set in hardwa re when spi transfers data from spixtxb to spixsr. automatically cleared in hardware when spixbuf is written to, loading spixtxb. bit 2 unimplemented: read as ? 0 ?
? 2009-2013 microchip technology inc. ds60001156h-page 215 pic32mx5xx/6xx/7xx bit 1 spitbf: spi transmit buffer full status bit 1 = transmit not yet started, spitxb is full 0 = transmit buffer is not full standard buffer mode: automatically set in hardware when the core writes to the spi buf location, loading spitxb. automatically cleared in hardware when the spi module transfers data from spitxb to spisr. enhanced buffer mode: set when cwptr + 1 = srptr; cleared otherwise bit 0 spirbf: spi receive buffer full status bit 1 = receive buffer, spixrxb is full 0 = receive buffer, spixrxb is not full standard buffer mode: automatically set in hardware when the spi module transfers data from spixsr to spixrxb. automatically cleared in hardware when spixbuf is read from, reading spixrxb. enhanced buffer mode: set when swptr + 1 = crptr; cleared otherwise register 17-2: spixstat: spi status register
pic32mx5xx/6xx/7xx ds60001156h-page 216 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 217 pic32mx5xx/6xx/7xx 18.0 inter-integrated circuit? (i 2 c?) the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard. figure 18-1 illustrates the i 2 c module block diagram. each i 2 c module has a 2-pin interface: the sclx pin is clock and the sdax pin is data. each i 2 c module offers the fo llowing key features: ?i 2 c interface supporting both master and slave operation ?i 2 c slave mode supports 7-bit and 10-bit addressing ?i 2 c master mode supports 7-bit and 10-bit addressing ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synchr onization for the i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) ?i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly ? provides support for address bit masking note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 24. ?inter- integrated circuit? (i 2 c?)? (ds60001116) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information.
pic32mx5xx/6xx/7xx ds60001156h-page 218 ? 2009-2013 microchip technology inc. figure 18-1: i 2 c? block diagram internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv
? 2009-2013 microchip technology inc. ds60001156h-page 219 pic32mx5xx/6xx/7xx 18.1 control registers register 18-1: i2c x con: i 2 c? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl sclrel strict a10m disslw smen 7:0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w- 0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen legend: hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: i 2 c enable bit (1) 1 = enables the i 2 c module and configures the sda and scl pins as serial port pins 0 = disables the i 2 c module; all i 2 c pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation when device enters idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). cleared by hardware at the beginning of a slave transmission and at the end of slave reception. if stren = 0 : bit is r/s (softwar e can only write ? 1 ? to release clock). cleared by hardware at the beginning of slave transmission. bit 11 strict: strict i 2 c reserved address rule enable bit 1 = strict reserved addressing is enforced. device does not respond to reserved address space or generate addresses in reserved address space. 0 = strict i 2 c reserved address rule is not enabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds compliant with smbus specification 0 = disable smbus input thresholds note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx5xx/6xx/7xx ds60001156h-page 220 ? 2009-2013 microchip technology inc. bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the so ftware initiates an acknowledge sequence. 1 = send nack during an acknowledge 0 = send ack during an acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. hardware clear at end of ma ster acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence. 0 = repeated start condition is not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition is not in progress register 18-1: i2c x con: i 2 c? control register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2009-2013 microchip technology inc. ds60001156h-page 221 pic32mx5xx/6xx/7xx register 18-2: i2c x stat: i 2 c? status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0, hsc r-0, hsc u-0 u-0 u-0 r/ c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 7:0 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d_a p s r_w rbf tbf legend: hs = set by hardware hsc = hardware set/cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared c = clearable bit bit 31-16 unimplemented: read as ? 0 ? bit 15 ackstat: acknowledge status bit (when operating as i 2 c master, applicable to master transmit operation) this bit is set or cleared by hardware at the end of a slave acknowledge. 1 = nack received from slave 0 = ack received from slave bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) this bit is set by hardware at the beginning of a master transmission, and is cleared by hardware at the end of a slave acknowledge. 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit this bit is set by hardware at the detection of a bus collision. 1 = a bus collision has been detec ted during a master operation 0 = no collision bit 9 gcstat: general call status bit this bit is set by hardware when the address matches the general call address, and is cleared by hardware clear at a stop detection. 1 = general call address was received 0 = general call address was not received bit 8 add10: 10-bit address status bit this bit is set by hardware upon a match of the 2nd by te of the matched 10-bit address, and is cleared by hardware at a stop detection. 1 = 10-bit address was matched 0 = 10-bit address was not matched bit 7 iwcol: write collision detect bit this bit is set by hardware at the occurrence of a write to i2cxtrn while busy (cleared by software). 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision bit 6 i2cov: receive overflow flag bit this bit is set by hardware at an attempt to tr ansfer i2cxrsr to i2cxrcv (cleared by software). 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow
pic32mx5xx/6xx/7xx ds60001156h-page 222 ? 2009-2013 microchip technology inc. bit 5 d_a: data/address bit (when operating as i 2 c slave) this bit is cleared by hardware upon a device address match, and is set by hardware by reception of the slave byte. 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address bit 4 p: stop bit this bit is set or cleared by hardware when a start, repeated start, or stop condition is detected. 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit this bit is set or cleared by hardware when a start, repeated start, or stop condition is detected. 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last bit 2 r_w: read/write information bit (when operating as i 2 c slave) this bit is set or cleared by hardware after reception of an i 2 c device address byte. 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave bit 1 rbf: receive buffer full status bit this bit is set by hardware when the i2cxrcv register is written with a received byte, and is cleared by hardware when software reads i2cxrcv. 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty bit 0 tbf: transmit buffer full status bit this bit is set by hardware when software writes to the i2cxtrn register, and is cleared by hardware upon completion of data transmission. 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty register 18-2: i2c x stat: i 2 c? status register (continued)
? 2009-2013 microchip technology inc. ds60001156h-page 223 pic32mx5xx/6xx/7xx 19.0 universal asynchronous receiver transmitter (uart) the uart module is one of the serial i/o modules available in pic32mx5xx/6xx/7xx family devices. the uart is a full-duplex, asynchronous communica- tion channel that communicates with peripheral devices and personal computers through protocols, such as rs-232, rs-485, lin 1.2 and irda ? . the module also supports the hardware flow control option, with uxcts and uxrts pins, and also includes an irda encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware auto-baud feature ? hardware flow control option ? fully integrated baud ra te generator (brg) with 16-bit prescaler ? baud rates ranging from 76 bps to 20 mbps at 80 mhz ? 8-level deep first-in-first-out (fifo) transmit data buffer ? 8-level deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt-only on address detect (ninth bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? lin 1.2 protocol support ? irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 19-1 illustrates a simplified block diagram of the uart module. figure 19-1: uart simplified block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. ?universal asynchronous receiver transmitter (uart)? (ds60001107) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts bclkx irda ? note: not all pins are available for all ua rt modules. refer to the device-specif ic pin diagram for more information (see ?pin diagrams? ).
pic32mx5xx/6xx/7xx ds60001156h-page 224 ? 2009-2013 microchip technology inc. figure 19-2 and figure 19-3 illustrate typical receive and transmit timing for the uart module. figure 19-2: uart reception figure 19-3: transmission (8-bit or 9-bit data) start 1 stop start 2 stop 4 start 5 stop 10 start 11 stop 13 cleared by software read to uxrxreg uxrx ridle oerr uxrxif urxisel = 00 uxrxif urxisel = 01 uxrxif urxisel = 10 char 1 char 2-4 char 5-10 char 11-13 cleared by software cleared by software start start bit 0 bit 1 stop write to tsr bclk/16 (shift clock) uxtx uxtxif uxtxif utxisel = 00 bit 1 uxtxreg utxisel = 01 uxtxif utxisel = 10 8 into txbuf pull from buffer
? 2009-2013 microchip technology inc. ds60001156h-page 225 pic32mx5xx/6xx/7xx 19.1 control registers register 19-1: uxmode: uartx mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 on (1) ?sidlirenrtsmd ?uen<1:0> 7:0 r/w-0 r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel<1:0> stsel legend: hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: uartx enable bit (1) 1 = uartx is enabled. uartx pins are controll ed by uartx as defined by uen<1:0> and utxen control bits. 0 = uartx is disabled. all uartx pins are controlled by corresponding bits in the portx, trisx and latx registers; uartx power consumption is minimal. bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation when device enters idle mode bit 12 iren: irda encoder and decoder enable bit 1 = irda is enabled 0 = irda is disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and uxbclk pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /uxbclk pins are controlled by corresponding bits in the portx register bit 7 wake: enable wake-up on start bit detect during sleep mode bit 1 = wake-up is enabled 0 = wake-up is disabled bit 6 lpback: uartx loopback mode select bit 1 = loopback mode is enabled 0 = loopback mode is disabled note 1: when using the 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx5xx/6xx/7xx ds60001156h-page 226 ? 2009-2013 microchip technology inc. bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next characte r ? requires reception of sync character (0x55); cleared by hardware upon completion 0 = baud rate measurement disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = high-speed mode ? 4x baud clock enabled 0 = standard speed mode ? 16x baud clock enabled bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop selection bit 1 = 2 stop bits 0 = 1 stop bit register 19-1: uxmode: uartx mode register (continued) note 1: when using the 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2009-2013 microchip technology inc. ds60001156h-page 227 pic32mx5xx/6xx/7xx register 19-2: uxsta: uartx status and control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?adm_en 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0 r-0 r-1 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/w-0, hs r-0 urxisel<1:0> adden ridle perr ferr oerr urxda legend: hs = set by hardware hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-25 unimplemented: read as ? 0 ? bit 24 adm_en: automatic address detect mode enable bit 1 = automatic address detect mode is enabled 0 = automatic address detect mode is disabled bit 23-16 addr<7:0>: automatic address mask bits when the adm_en bit is ? 1 ?, this value defines the address character to use for automatic address detection. bit 15-14 utxisel<1:0>: tx interrupt mode selection bits 11 = reserved, do not use 10 = interrupt is generated and asserted while the transmit buffer is empty 01 = interrupt is generated and asserted w hen all characters have been transmitted 00 = interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 utxinv: transmit polarity inversion bit if irda mode is disabled (i.e., iren (uxmode<12>) is ? 0 ?): 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if irda mode is enabled (i.e., iren (uxmode<12>) is ? 1 ?): 1 = irda encoded uxtx idle state is ? 1 ? 0 = irda encoded uxtx idle state is ? 0 ? bit 12 urxen: receiver enable bit 1 = uartx receiver is enabled. uxrx pin is controlled by uartx (if on = 1 ) 0 = uartx receiver is disabled. uxrx pin is ignored by the uartx module. uxrx pin is controlled by port. bit 11 utxbrk: transmit break bit 1 = send break on next transmission. start bit followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion. 0 = break transmission is disabled or completed bit 10 utxen: transmit enable bit 1 = uartx transmitter is enabled. uxtx pin is controlled by uartx (if on = 1 ) 0 = uartx transmitter is disabled . any pending transmission is aborted and buffer is reset. uxtx pin is controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at le ast one more character can be written
pic32mx5xx/6xx/7xx ds60001156h-page 228 ? 2009-2013 microchip technology inc. bit 8 trmt: transmit shift register is empty bit (read-only) 1 = transmit shift register is empty and transmit buf fer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmi ssion is in progress or queued in the transmit buffer bit 7-6 urxisel<1:0>: receive interrupt mode selection bit 11 = reserved 10 = interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters) 01 = interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters) 00 = interrupt flag bit is asserted while receive bu ffer is not empty (has at least 1 data character) bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled. if 9-bit mode is not selected, this control bit has no effect. 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = data is being received bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit. this bit is set in hardware and can only be cleared (= 0 ) in software. clearing a previously set oerr bit resets the receiver buffer and rsr to an empty state. 1 = receive buffer has overflowed 0 = receive buffer has not overflowed bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 19-2: uxsta: uartx status and control register (continued)
? 2009-2013 microchip technology inc. ds60001156h-page 229 pic32mx5xx/6xx/7xx 20.0 parallel master port (pmp) the pmp is a parallel 8-bi t/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. figure 20-1 shows the pmp module pinout and its connections to external devices. key features of the pmp module include: ? 8-bit and 16-bit interface ? up to 16 programmable address lines ? up to two chip select lines ? programmable strobe options - individual read and write strobes, or - read/wr ite strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? parallel slave port support - legacy addressable - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? operates during sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 20-1: pmp module pinout and connections to external devices note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?parallel master port (pmp)? (ds60001128) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: on 64-pin devices, the pmd<15:8> data pins are not available. pma<0> pma<14> pma<15> pmrd pmwr pmenb pmrd/pmwr pmcs1 pma<1> pma<13:2> pmall pmalh pmcs2 flash address bus data bus control lines pic32mx5xx/6xx/7xx lcd fifo microcontroller 16/8-bit data (with or without multiplexed addressing) up to 16-bit address parallel buffer pmd<15:8> (1) pmd<7:0> master port note 1: on 64-pin devices, data pins, pmd<15:8>, ar e not available in 16-bit master modes. eeprom sram
pic32mx5xx/6xx/7xx ds60001156h-page 230 ? 2009-2013 microchip technology inc. 20.1 control registers register 20-1: pmcon: parall el port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ?sidl adrmux<1:0> pmpttl ptwren ptrden 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 csf<1:0> (2) alp (2) ?cs1p (2) ? wrsp rdsp legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: parallel master port enable bit (1) 1 = pmp is enabled 0 = pmp is disabled, no off-chip access performed bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation when device enters idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = lower 8 bits of address are multiplexed on pmd<7:0> pins; upper 8 bits are not used 10 = all 16 bits of address are multiplexed on pmd<7:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper bits are on pma<10:8> and pma<14> 00 = address and data appear on separate pins bit 10 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffer bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port is enabled 0 = pmwr/pmenb port is disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port is enabled 0 = pmrd/pmwr port is disabled bit 7-6 csf<1:0>: chip select function bits (2) 11 = reserved 10 = pmcs1 functions as chip select 01 = pmcs1 functions as address bit 14 00 = pmcs1 functions as address bit 14 note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines.
? 2009-2013 microchip technology inc. ds60001156h-page 231 pic32mx5xx/6xx/7xx bit 5 alp: address latch polarity bit (2) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 unimplemented: read as ? 0 ? bit 3 cs1p: chip select 0 polarity bit (2) 1 = active-high (pmcs1) 0 = active-low (pmcs1 ) bit 2 unimplemented: read as ? 0 ? bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 20-1: pmcon: parallel po rt control register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines.
pic32mx5xx/6xx/7xx ds60001156h-page 232 ? 2009-2013 microchip technology inc. register 20-2: pmmode: parallel port mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> ? mode<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1) waitm<3:0> (1) waite<1:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 busy: busy bit (only master mode) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = reserved 10 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) or on a read or write operation when pma<1:0> = 11 (only addressable slave mode) 01 = interrupt generated at the end of the read/write cycle 00 = interrupt is not generated bit 12-11 incm<1:0>: increment mode bits 11 = slave mode read and write buffers auto-increment (only pmmode<1:0> = 00 ) 10 = decrement addr<10:2> and addr <14> by 1 every read/write cycle (2) 01 = increment addr<10:2> and addr< 14> by 1 every read/write cycle (2) 00 = no increment or decrement of address bit 10 unimplemented: read as ? 0 ? bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcs1, pmrd/pmwr, pmenb, pma , and pmd<7:0>) 10 = master mode 2 (pmcs1, pmrd, pmwr, pma, and pmd<7:0>) 01 = enhanced slave mode, control signals (pm rd, pmwr, pmcs1, pmd<7:0>, and pma<1:0>) 00 = legacy parallel slave port, control si gnals (pmrd, pmwr, pmcs1, and pmd<7:0>) bit 7-6 waitb<1:0>: data setup to read/write strobe wait states bits (1) 11 = data wait of 4 t pb ; multiplexed address phase of 4 t pb 10 = data wait of 3 t pb ; multiplexed address phase of 3 t pb 01 = data wait of 2 t pb ; multiplexed address phase of 2 t pb 00 = data wait of 1 t pb ; multiplexed address phase of 1 t pb (default) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1.
? 2009-2013 microchip technology inc. ds60001156h-page 233 pic32mx5xx/6xx/7xx bit 5-2 waitm<3:0>: data read/write strobe wait states bits (1) 1111 = wait of 16 t pb ? ? ? 0001 = wait of 2 t pb 0000 = wait of 1 t pb (default) bit 1-0 waite<1:0>: data hold after read/write strobe wait states bits (1) 11 = wait of 4 t pb 10 = wait of 3 t pb 01 = wait of 2 t pb 00 = wait of 1 t pb (default) for read operations: 11 = wait of 3 t pb 10 = wait of 2 t pb 01 = wait of 1 t pb 00 = wait of 0 t pb (default) register 20-2: pmmode: parallel port mode register (continued) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1.
pic32mx5xx/6xx/7xx ds60001156h-page 234 ? 2009-2013 microchip technology inc. register 20-3: pmaddr: para llel port address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?cs1 ? ? ? addr<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 cs1: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive (pin functions as pma<14>) bit 13-11 unimplemented: read as ? 0 ? bit 10-0 addr<10:0>: destination address bits
? 2009-2013 microchip technology inc. ds60001156h-page 235 pic32mx5xx/6xx/7xx register 20-4: pmaen: paralle l port pin enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?pten14 ? ? ?pten<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 15-14 pten14: pmcs1 strobe enable bits 1 = pma14 functions as either pma14 or pmcs1 (1) 0 = pma14 functions as port i/o bit 13-11 unimplemented: read as ? 0 ? bit 10-2 pten<10:2>: pmp address port enable bits 1 = pma<10:2> function as pmp address lines 0 = pma<10:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall (2) 0 = pma1 and pma0 pads function as port i/o note 1: the use of this pin as pma14 or cs1 is selected by the csf<1:0> bits in the pmcon register. 2: the use of these pins as pma1/p ma0 or pmalh/pmall depends on the address/data multiplex mode selected by bits adrmux<1:0> in the pmcon register.
pic32mx5xx/6xx/7xx ds60001156h-page 236 ? 2009-2013 microchip technology inc. register 20-5: pmstat: parallel port status register (only slave modes) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0, hsc u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ? ? ib3fib2fib1fib0f 7:0 r-1 r/w-0, hsc u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ? ? ob3e ob2e ob1e ob0e legend: hsc = set by hardware; cleared by software r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte buffer occurred (must be cleared in software) 0 = an overflow has not occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ibxf: input buffer ?x? status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte buffer (must be cleared in software) 0 = an underflow has not occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 obxe: output buffer ?x? status empty bits 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted
? 2009-2013 microchip technology inc. ds60001156h-page 237 pic32mx5xx/6xx/7xx 21.0 real-time clock and calendar (rtcc) the pic32 rtcc module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low-power optimization provides extended battery lifetime whil e keeping track of time. a simplified block diagram of the rtcc module is illustrated in figure 21-1 . key features of the rtcc module include: ? time: hours, minutes and seconds ? 24-hour format (military time) ? visibility of one-half second period ? provides calendar: weekday, date, month and year ? alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat: chime ? year range: 2000 to 2099 ? leap year correction ? bcd format for smalle r firmware overhead ? optimized for long-term battery operation ? fractional second synchronization ? user calibration of the clock crystal frequency with auto-adjust ? calibration range: ? 0.66 seconds error per month ? calibrates up to 260 ppm of crystal error ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin figure 21-1: rtcc block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. ?real-time clock and calendar (rtcc)? (ds60001125) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. seconds pulse rtcc prescalers rtcc timer comparator compare registers repeat counter year, mth, day wkday hr, min, sec mth, day wkday hr, min, sec with masks rtcc interrupt logic alarm event 32.768 khz input from secondary 0.5s alarm pulse rtcc interrupt rtcval alrmval rtcc pin rtcoe oscillator (s osc )
pic32mx5xx/6xx/7xx ds60001156h-page 238 ? 2009-2013 microchip technology inc. 21.1 control registers register 21-1: rtccon: rtc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?cal<9:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1,2) ?sidl ? ? ? ? ? 7:0 r/w-0 r-0 u-0 u-0 r/w-0 r-0 r-0 r/w-0 rtsecsel (3) rtcclkon ? ?rtcwren (4) rtcsync halfsec (5) rtcoe legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as ? 0 ? bit 25-16 cal<9:0>: rtc drift calibration bits, which contain a signed 10-bit integer value 1111111111 = minimum negative adjustment, subtra cts 1 rtc clock pulse every one minute ? ? ? 1000000000 = minimum negative adjustment, subtra cts 512 clock pulses every one minute 0111111111 = maximum positive adjustment, adds 511 rtc clock pulses every one minute ? ? ? 0000000001 = minimum positive adjustment, adds 1 rtc clock pulse every one minute 0000000000 = no adjustment bit 15 on: rtcc on bit (1,2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = disables the pbclk to the rtcc when cpu enters in idle mode 0 = continue normal operation in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 rtsecsel: rtcc seconds clock output select bit (3) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 6 rtcclkon: rtcc clock enable status bit 1 = rtcc clock is actively running 0 = rtcc clock is not running bit 5-4 unimplemented: read as ? 0 ? note 1: the on bit is only writable when rtcwren = 1 . 2: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 3: requires rtcoe = 1 (rtccon<0>) for the output to be active. 4: the rtcwren bit can only be set when the write sequence is enabled. 5: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). note: this register is only rese t on a power-on reset (por).
? 2009-2013 microchip technology inc. ds60001156h-page 239 pic32mx5xx/6xx/7xx bit 3 rtcwren: rtc value registers write enable bit (4) 1 = rtc value registers can be written to by the user 0 = rtc value registers are locked out from being written to by the user bit 2 rtcsync: rtcc value registers read synchronization bit 1 = rtc value registers can change while reading, due to a rollover ripple that results in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtc value registers can be read wi thout concern about a rollover ripple bit 1 halfsec: half-second status bit (5) 1 = second half period of a second 0 = first half period of a second bit 0 rtcoe: rtcc output enable bit 1 = rtcc clock output is enabled (clock presented onto an i/o) 0 = rtcc clock output is disabled register 21-1: rtccon: rtc co ntrol register (continued) note 1: the on bit is only writable when rtcwren = 1 . 2: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 3: requires rtcoe = 1 (rtccon<0>) for the output to be active. 4: the rtcwren bit can only be set when the write sequence is enabled. 5: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). note: this register is only reset on a power-on reset (por).
pic32mx5xx/6xx/7xx ds60001156h-page 240 ? 2009-2013 microchip technology inc. register 21-2: rtcalrm: rtc alarm control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen (1,2) chime (2) piv (2) alrmsync (3) amask<3:0> (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 alrmen: alarm enable bit (1,2) 1 = alarm is enabled 0 = alarm is disabled bit 14 chime: chime enable bit (2) 1 = chime is enabled ? arpt<7:0> is allowed to rollover from 0x00 to 0xff 0 = chime is disabled ? arpt<7:0> stops once it reaches 0x00 bit 13 piv: alarm pulse initial value bit (3) when alrmen = 0 , piv is writable and determines the initial value of the alarm pulse. when alrmen = 1 , piv is read-only and returns the state of the alarm pulse. bit 12 alrmsync: alarm sync bit (3) 1 = arpt<7:0> and alrmen may change as a result of a half second rollover during a read. the arpt must be read repeatedly until the same valu e is read twice. this must be done since multiple bits may be changing, which are then synchronized to the pb clock domain. 0 = arpt<7:0> and alrmen can be read without concer ns of rollover because the prescaler is > 32 rtc clocks away from a half-second rollover bit 11-8 amask<3:0>: alarm mask configuration bits (2) 1111 = reserved ? ? ? 1010 = reserved 1001 = once a year (except when configured for february 29, once every four years) 1000 = once a month 0111 = once a week 0110 = once a day 0101 = every hour 0100 = every 10 minutes 0011 = every minute 0010 = every 10 seconds 0001 = every second 0000 = every half-second note 1: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 3: this assumes a cpu read will execute in less than 32 pbclks. note: this register is only rese t on a power-on reset (por).
? 2009-2013 microchip technology inc. ds60001156h-page 241 pic32mx5xx/6xx/7xx bit 7-0 arpt<7:0>: alarm repeat counter value bits (2) 11111111 = alarm will trigger 256 times ? ? ? 00000000 = alarm will trigger one time the counter decrements on any alarm event. the counte r only rolls over from 0x00 to 0xff if chime = 1 . register 21-2: rtcalrm: rtc alarm control register (continued) note 1: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 3: this assumes a cpu read will execute in less than 32 pbclks. note: this register is only reset on a power-on reset (por).
pic32mx5xx/6xx/7xx ds60001156h-page 242 ? 2009-2013 microchip technology inc. register 21-3: rtctime: rtc time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary-coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary-coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary-coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary-coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary-coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary-coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ? note: this register is only writable when rtcwren = 1 (rtccon<3>).
? 2009-2013 microchip technology inc. ds60001156h-page 243 pic32mx5xx/6xx/7xx register 21-4: rtcdate: rtc date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x year10<3:0> year01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 year10<3:0>: binary-coded decimal value of years bits, 10 digits bit 27-24 year01<3:0>: binary-coded decimal value of years bits, 1 digit bit 23-20 month10<3:0>: binary-coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary-coded decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary-coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary-coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary-coded decimal value of weekdays bits,1 digit; contains a value from 0 to 6 note: this register is only writable when rtcwren = 1 (rtccon<3>).
pic32mx5xx/6xx/7xx ds60001156h-page 244 ? 2009-2013 microchip technology inc. register 21-5: alrmtime: alarm time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ?
? 2009-2013 microchip technology inc. ds60001156h-page 245 pic32mx5xx/6xx/7xx register 21-6: alrmdate: alarm date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<1:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-20 month10<3:0>: binary coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary coded decimal value of months bits , 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
pic32mx5xx/6xx/7xx ds60001156h-page 246 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 247 pic32mx5xx/6xx/7xx 22.0 10-bit analog-to-digital converter (adc) the pic32mx5xx/6xx/7xx 10 -bit analog-to-digital converter (adc) includes the following features: ? successive approximation register (sar) conversion ? up to 1 msps conversion speed ? up to 16 analog input pins ? external voltage reference input pins ? one unipolar, differential sample and hold (s&h) circuit ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? eight conversion result format options ? operation during sleep and idle modes a block diagram of the 10-bit adc is illustrated in figure 22-1 . the 10-bit adc has up to 16 analog input pins, designated an0-an15. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. the analog inputs are connected through two multi- plexers (muxs) to one s&h. the analog input muxs can be switched between two sets of analog inputs between conversions. unipolar differential conversions are possible on all channels , other than the pin used as the reference, using a reference input pin (see figure 22-1 ). the analog input scan mode sequentially converts user-specified channels. a control register specifies which analog input channels will be included in the scanning sequence. the 10-bit adc is connected to a 16-word result buffer. each 10-bit result is converted to one of eight 32-bit output formats when it is read from the result buffer. figure 22-1: adc1 module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?10-bit analog-to-digital converter (adc)? (ds60001104) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. sar adc s&h adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0 an15 an1 v refl ch0sb<4:0> ch0na ch0nb + - ch0sa<4:0> channel scan cscna alternate v ref + (1) av dd av ss v ref - (1) note 1: v ref + and v ref - inputs can be multiplexed with other analog inputs. input selection v refh v refl vcfg<2:0>
pic32mx5xx/6xx/7xx ds60001156h-page 248 ? 2009-2013 microchip technology inc. figure 22-2: adc conversion clock period block diagram 1 0 t pb adc conversion clock multiplier 2, 4,..., 512 adrc t ad 8 adcs<7:0> frc ? 2
? 2009-2013 microchip technology inc. ds60001156h-page 249 pic32mx5xx/6xx/7xx 22.1 control registers register 22-1: ad1con1: adc control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 on (1) ?sidl ? ? form<2:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0, hsc r/c-0, hsc ssrc<2:0> clrasam ? asam samp (2) done (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: adc operating mode bit (1) 1 = adc module is operating 0 = adc module is not operating bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 form<2:0>: data output format bits 111 = signed fractional 32-bit (dout = sddd dddd dd00 0000 0000 0000 0000 ) 110 = fractional 32-bit (dout = dddd dddd dd00 0000 0000 0000 0000 0000 ) 101 = signed integer 32-bit (dout = ssss ssss ssss ssss ssss sssd dddd dddd ) 100 = integer 32-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) 011 = signed fractional 16-bit (dout = 0000 0000 0000 0000 sddd dddd dd00 0000 ) 010 = fractional 16-bit (dout = 0000 0000 0000 0000 dddd dddd dd00 0000 ) 001 = signed integer 16-bit (dout = 0000 0000 0000 0000 ssss sssd dddd dddd ) 000 = integer 16-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc<2:0> = 000 , software can write a ?0? to end sampling and start conversion. if ssrc<2:0> ? ? ? 000 ?, this bit is automatically cleared by har dware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clea red by hardware at the start of a new conversion.
pic32mx5xx/6xx/7xx ds60001156h-page 250 ? 2009-2013 microchip technology inc. bit 7-5 ssrc<2:0>: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto convert) 110 = reserved 101 = reserved 100 = reserved 011 = ctmu ends sampling and starts conversion 010 = timer 3 period match ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing the samp bit ends sampling and starts conversion bit 4 clrasam: stop conversion sequence bit (when the first adc interrupt is generated) 1 = stop conversions when the first adc interrupt is generated. hardwa re clears the asam bit when the adc interrupt is generated. 0 = normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 unimplemented: read as ? 0 ? bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conver sion completes; samp bi t is automatically set 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit (2) 1 = the adc s&h circuit is sampling 0 = the adc s&h circuit is holding when asam = 0 , writing ? 1 ? to this bit starts sampling. when ssrc<2:0> = 000 , writing ? 0 ? to this bit will end sampling and start conversion. bit 0 done: analog-to-digital conversion status bit (3) clearing this bit will not affect any operation in progress. 1 = analog-to-digital conversion is done 0 = analog-to-digital conversion is not done or has not started register 22-1: ad1con1: adc cont rol register 1 (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc<2:0> = 000 , software can write a ?0? to end sampling and start conversion. if ssrc<2:0> ? ? ? 000 ?, this bit is automatically cleared by har dware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clear ed by hardware at the start of a new conversion.
? 2009-2013 microchip technology inc. ds60001156h-page 251 pic32mx5xx/6xx/7xx register 22-2: ad1con2: adc control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 vcfg<2:0> offcal ?cscna ? ? 7:0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-13 vcfg<2:0>: voltage reference configuration bits bit value v refh v refl 1xx av dd avss 011 external v ref + pin external v ref - pin 010 av dd external v ref - pin 001 external v ref + pin av ss 000 av dd avss bit 12 offcal: input offset calibration mode select bit 1 = enable offset calibration mode positive and negative inputs of the s&h circuit are connected to v refl . 0 = disable offset calibration mode the inputs to the s&h circuit are controlled by ad1chs or ad1cssl. bit 11 unimplemented: read as ? 0 ? bit 10 cscna: input scan select bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit only valid when bufm = 1 . 1 = adc is currently filling buffer 0x8-0xf, user should access data in 0x0-0x7 0 = adc is currently filling buffer 0x0-0x7, user should access data in 0x8-0xf bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16 th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15 th sample/convert sequence ? ? ? 0001 = interrupts at the completion of conversion for each 2 nd sample/convert sequence 0000 = interrupts at the completion of conv ersion for each sample/convert sequence bit 1 bufm: adc result buffer mode select bit 1 = buffer configured as two 8-word buffers, adc1buf7-adc1buf0, adc1buff-adcbuf8 0 = buffer configured as one 16-word buffer adc1buff-adc1buf0 bit 0 alts: alternate input sample mode select bit 1 = uses sample a input multiplexer settings for first sample, and then alternates between sample b and sample a input multiplexer settings for all subsequent samples 0 = always use sample a input multiplexer settings
pic32mx5xx/6xx/7xx ds60001156h-page 252 ? 2009-2013 microchip technology inc. register 22-3: ad1con3: adc control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w r/w-0 adcs<7:0> (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 adrc: adc conversion clock source bit 1 = clock derived from frc 0 = clock derived from peripheral bus clock (pbclk) bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto-sample time bits (1) 11111 =31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad (not allowed) bit 7-0 adcs<7:0>: adc conversion clock select bits (2) 11111111 =t pb ? 2 ? (adcs<7:0> + 1) = 512 ? t pb = t ad ? ? ? 00000001 =t pb ? 2 ? (adcs<7:0> + 1) = 4 ? t pb = t ad 00000000 =t pb ? 2 ? (adcs<7:0> + 1) = 2 ? t pb = t ad note 1: this bit is only used if the ss rc<2:0> bits (ad1con1<7:5>) = 111 . 2: this bit is not used if the adrc bit (ad1con3<15>) = 1 .
? 2009-2013 microchip technology inc. ds60001156h-page 253 pic32mx5xx/6xx/7xx register 22-4: ad1chs: adc input select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ? ch0sb<3:0> 23:16 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ? ch0sa<3:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ch0nb: negative input select bit for sample b 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 30-28 unimplemented: read as ? 0 ? bit 27-24 ch0sb<3:0>: positive input select bits for sample b 1111 = channel 0 positive input is an15 ? ? ? 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 23 ch0na: negative input select bit fo r sample a multiplexer setting 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 22-20 unimplemented: read as ? 0 ? bit 19-16 ch0sa<3:0>: positive input select bits fo r sample a multiplexer setting 1111 = channel 0 positive input is an15 ? ? ? 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 15-0 unimplemented: read as ? 0 ?
pic32mx5xx/6xx/7xx ds60001156h-page 254 ? 2009-2013 microchip technology inc. register 22-5: ad1cssl: adc input scan select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 cssl<15:0>: adc input pin scan selection bits (1) 1 = select anx for input scan 0 = skip anx for input scan note 1: cssl = anx, where ?x? = 0-15.
? 2009-2013 microchip technology inc. ds60001156h-page 255 pic32mx5xx/6xx/7xx 23.0 controller area network (can) the controller area network (can) module supports the following key features: ? standards compliance: - full can 2.0b compliance - programmable bit rate up to 1 mbps ? message reception and transmission: - 32 message fifos - each fifo can have up to 32 messages for a total of 1024 messages - fifo can be a transmit message fifo or a receive message fifo - user-defined priority levels for message fifos used for transmission - 32 acceptance filters for message filtering - four acceptance filter mask registers for message filtering - automatic response to remote transmit request - devicenet? addressing support ? additional features: - loopback, listen all messages, and listen only modes for self-test, system diagnostics and bus monitoring - low-power operating modes - can module is a bus master on the pic32 system bus - use of dma is not required - dedicated time-stamp timer - dedicated dma channels - data-only message reception mode figure 23-1 illustrates the general structure of the can module. figure 23-1: pic32 can module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 34. ?controller area network (can)? (ds60001154) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 fifo0 fifo1 fifo31 system ram up to 32 message buffers can message fifo (up to 32 fifos) message buffer size 2 or 4 words system bus cpu can module 32 filters 4 masks cxtx cxrx
pic32mx5xx/6xx/7xx ds60001156h-page 256 ? 2009-2013 microchip technology inc. register 23-1: cicon: c an module control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 s/hc-0 r/w-1 r/w-0 r/w-0 ? ? ? ? abat reqop<2:0> 23:16 r-1 r-0 r-0 r/w-0 u-0 u-0 u-0 u-0 opmod<2:0> cancap ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 r-0 u-0 u-0 u-0 on (1) ?sidle ? canbusy ? ? ? 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dncnt<4:0> legend: hc = hardware clear s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 unimplemented: read as ? 0 ? bit 27 abat: abort all pending transmissions bit 1 = signal all transmit buffers to abort transmission 0 = module will clear this bit when all transmissions aborted bit 26-24 reqop<2:0>: request operation mode bits 111 = set listen all messages mode 110 = reserved 101 = reserved 100 = set configuration mode 011 = set listen only mode 010 = set loopback mode 001 = set disable mode 000 = set normal operation mode bit 23-21 opmod<2:0>: operation mode status bits 111 = module is in listen all messages mode 110 = reserved 101 = reserved 100 = module is in configuration mode 011 = module is in listen only mode 010 = module is in loopback mode 001 = module is in disable mode 000 = module is in normal operation mode bit 20 cancap: can message receive time stamp timer capture enable bit 1 = cantmr value is stored on valid message reception and is stored with the message 0 = disable can message receive time stamp timer capture and stop cantmr to conserve power bit 19-16 unimplemented: read as ? 0 ? bit 15 on: can on bit (1) 1 = can module is enabled 0 = can module is disabled bit 14 unimplemented: read as ? 0 ? note 1: if the user application clears this bit, it may take a number of cycles before t he can module completes the current transaction and responds to this request. the user application should poll the canbusy bit to verify that the request has been honored.
? 2009-2013 microchip technology inc. ds60001156h-page 257 pic32mx5xx/6xx/7xx bit 13 sidle: can stop in idle bit 1 = can stops operation wh en system enters idle mode 0 = can continues operation w hen system enters idle mode bit 12 unimplemented: read as ? 0 ? bit 11 canbusy: can module is busy bit 1 = the can module is active 0 = the can module is completely disabled bit 10-5 unimplemented: read as ? 0 ? bit 4-0 dncnt<4:0>: device net filter bit number bits 10011-11111 = invalid selection (compare up to 18-bits of data with eid) 10010 = compare up to data byte 2 bit 6 with eid17 (cirxfn<17>) ? ? ? 00001 = compare up to data byte 0 bit 7 with eid0 (cirxfn<0>) 00000 = do not compare data bytes register 23-1: cicon: can module control register (continued) note 1: if the user application clears this bit, it may take a number of cycles before the can module completes the current transaction and responds to this request. the user application should poll the canbusy bit to verify that the request has been honored.
pic32mx5xx/6xx/7xx ds60001156h-page 258 ? 2009-2013 microchip technology inc. register 23-2: cicfg: can baud rate configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? wakfil ? ? ? seg2ph<2:0> (1,4) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 seg2phts (1) sam (2) seg1ph<2:0> prseg<2:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw<1:0> (3) brp<5:0> legend: hc = hardware clear s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-23 unimplemented: read as ? 0 ? bit 22 wakfil: can bus line filter enable bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 21-19 unimplemented: read as ? 0 ? bit 18-16 seg2ph<2:0>: phase buffer segment 2 bits (1,4) 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q bit 15 seg2phts: phase segment 2 time select bit (1) 1 = freely programmable 0 = maximum of seg1ph or information processing time, whichever is greater bit 14 sam: sample of the can bus line bit (2) 1 = bus line is sampled three times at the sample point 0 = bus line is sampled once at the sample point bit 13-11 seg1ph<2:0>: phase buffer segment 1 bits (4) 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q note 1: seg2ph ?? seg1ph. if seg2phts is clear, seg2ph will be set automatically. 2: 3 time bit sampling is not allowed for brp < 2. 3: sjw ? seg2ph. 4: the time quanta per bit must be greater than 7 (that is, t qbit > 7). note: this register can only be modified when the ca n module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100) .
? 2009-2013 microchip technology inc. ds60001156h-page 259 pic32mx5xx/6xx/7xx bit 10-8 prseg<2:0>: propagation time segment bits (4) 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q bit 7-6 sjw<1:0>: synchronization jump width bits (3) 11 = length is 4 x t q 10 = length is 3 x t q 01 = length is 2 x t q 00 = length is 1 x t q bit 5-0 brp<5:0>: baud rate prescaler bits 111111 = t q = (2 x 64)/f sys 111110 = t q = (2 x 63)/f sys ? ? ? 000001 = t q = (2 x 2)/f sys 000000 = t q = (2 x 1)/f sys register 23-2: cicfg: can baud rate configuration regi ster (continued) note 1: seg2ph ?? seg1ph. if seg2phts is clear, seg2ph will be set automatically. 2: 3 time bit sampling is not allowed for brp < 2. 3: sjw ? seg2ph. 4: the time quanta per bit must be greater than 7 (that is, t qbit > 7). note: this register can only be modified when the ca n module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100) .
pic32mx5xx/6xx/7xx ds60001156h-page 260 ? 2009-2013 microchip technology inc. register 23-3: ciint: can interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ivrie wakie cerrie serrie rbovie ? ? ? 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? modie ctmrie rbie tbie 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ivrif wakif cerrif serrif (1) rbovif ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? modif ctmrif rbif tbif legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ivrie: invalid message received interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 30 wakie: can bus activity wake-up interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 29 cerrie: can bus error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 28 serrie: system error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 27 rbovie: receive buffer overflow interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 26-20 unimplemented: read as ? 0 ? bit 19 modie: mode change interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 18 ctmrie: can timestamp timer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 17 rbie: receive buffer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 16 tbie: transmit buffer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 15 ivrif: invalid message receiv ed interrupt flag bit 1 = an invalid messages interrupt has occurred 0 = an invalid message interrupt has not occurred note 1: this bit can only be cleared by turning the can module off and on by clearing or setting the on bit (cicon<15>).
? 2009-2013 microchip technology inc. ds60001156h-page 261 pic32mx5xx/6xx/7xx bit 14 wakif: can bus activity wake-up interrupt flag bit 1 = a bus wake-up activity interrupt has occurred 0 = a bus wake-up activity interrupt has not occurred bit 13 cerrif: can bus error interrupt flag bit 1 = a can bus error has occurred 0 = a can bus error has not occurred bit 12 serrif: system error in terrupt flag bit 1 = a system error occurred (typically an il legal address was presented to the system bus) 0 = a system error has not occurred bit 11 rbovif: receive buffer overflow interrupt flag bit 1 = a receive buffer overflow has occurred 0 = a receive buffer overflow has not occurred bit 10-4 unimplemented: read as ? 0 ? bit 3 modif: can mode change interrupt flag bit 1 = a can module mode change has occurred (opmod<2:0> has changed to reflect reqop) 0 = a can module mode change has not occurred bit 2 ctmrif: can timer overflow interrupt flag bit 1 = a can timer (cantmr) overflow has occurred 0 = a can timer (cantmr) overflow has not occurred bit 1 rbif: receive buffer interrupt flag bit 1 = a receive buffer interrupt is pending 0 = a receive buffer interrupt is not pending bit 0 tbif: transmit buffer interrupt flag bit 1 = a transmit buffer interrupt is pending 0 = a transmit buffer interrupt is not pending register 23-3: ciint: can interrupt register (continued) note 1: this bit can only be cleared by turning the can module off and on by clearing or setting the on bit (cicon<15>).
pic32mx5xx/6xx/7xx ds60001156h-page 262 ? 2009-2013 microchip technology inc. register 23-4: civec: can interrupt code register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? filhit<4:0> 7:0 u-0 r-1 r-0 r-0 r-0 r-0 r-0 r-0 ?icode<6:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as ? 0 ? bit 12-8 filhit<4:0>: filter hit number bit 11111 = filter 31 11110 = filter 30 ? ? ? 00001 = filter 1 00000 = filter 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 icode<6:0>: interrupt flag code bits (1) 1111111 = reserved ? ? ? 1001001 = reserved 1001000 = invalid message received (ivrif) 1000111 = can module mode change (modif) 1000110 = can timestamp timer (ctmrif) 1000101 = bus bandwidth error (serrif) 1000100 = address error interrupt (serrif) 1000011 = receive fifo overflow interrupt (rbovif) 1000010 = wake-up interrupt (wakif) 1000001 = error interrupt (cerrif) 1000000 = no interrupt 0111111 = reserved ? ? ? 0100000 = reserved 0011111 = fifo31 interrupt (cifstat<31> set) 0011110 = fifo30 interrupt (cifstat<30> set) ? ? ? 0000001 = fifo1 interrupt (cifstat<1> set) 0000000 = fifo0 interrupt (cifstat<0> set) note 1: these bits are only updated for enabled interrupts.
? 2009-2013 microchip technology inc. ds60001156h-page 263 pic32mx5xx/6xx/7xx register 23-5: citrec: can transmi t/receive error count register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? txbo txbp rxbp txwarn rxwarn ewarn 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 terrcnt<7:0> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rerrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-22 unimplemented: read as ? 0 ? bit 21 txbo: transmitter in error state bus off (terrcnt ? 256) bit 20 txbp: transmitter in error state bus passive (terrcnt ? 128) bit 19 rxbp: receiver in error state bus passive (rerrcnt ? 128) bit 18 txwarn: transmitter in error state warning (128 > terrcnt ? 96) bit 17 rxwarn: receiver in error state warning (128 > rerrcnt ? 96) bit 16 ewarn: transmitter or receiver is in error state warning bit 15-8 terrcnt<7:0>: transmit error counter bit 7-0 rerrcnt<7:0>: receive error counter register 23-6: cifstat: can fifo status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fifoip16 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 fifoip<31:0>: fifon interrupt pending bits 1 = one or more enabled fifo interrupts are pending 0 = no fifo interrupts are pending
pic32mx5xx/6xx/7xx ds60001156h-page 264 ? 2009-2013 microchip technology inc. register 23-7: cirxovf: can receive fifo overflow status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 rxovf<31:0>: fifon receive overflow interrupt pending bit 1 = fifo has overflowed 0 = fifo has not overflowed register 23-8: citmr: can timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cants<15:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cants<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cantspre<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cantspre<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 cants<15:0>: can time stamp timer bits this is a free-running timer that increments every cantspre system clocks when the cancap bit (cicon<20>) is set. bit 15-0 cantspre<15:0>: can time stamp timer prescaler bits 1111 1111 1111 1111 = can time stamp timer (cants) increments every 65,535 system clocks ? ? ? 0000 0000 0000 0000 = can time stamp timer (cants) increments every system clock note 1: citmr will be paused when cancap = 0 . 2: the citmr prescaler count will be reset on any write to citmr (cantspre will be unaffected).
? 2009-2013 microchip technology inc. ds60001156h-page 265 pic32mx5xx/6xx/7xx register 23-9: cirxmn: can acceptance filter mask ?n? register (n = 0, 1, 2 or 3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sid<10:3> 23:16 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 sid<2:0> ?mide ? eid<17:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eid<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eid<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-21 sid<10:0>: standard identifier bits 1 = include the sidx bit in filter comparison 0 = the sidx bit is a ?don?t care? in filter operation bit 20 unimplemented: read as ? 0 ? bit 19 mide: identifier receive mode bit 1 = match only message types (standard/extended addr ess) that correspond to the exid bit in filter 0 = match either standard or extended address message if filters match (that is, if (filter si d) = (message sid) or if (filter sid/eid) = (message sid/eid)) bit 18 unimplemented: read as ? 0 ? bit 17-0 eid<17:0>: extended identifier bits 1 = include the eidx bit in filter comparison 0 = the eidx bit is a ?don?t care? in filter operation note: this register can only be modified when the can module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100 ).
pic32mx5xx/6xx/7xx ds60001156h-page 266 ? 2009-2013 microchip technology inc. register 23-10: cifltcon0: can filter control register 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten3 msel3<1:0> fsel3<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten2 msel2<1:0> fsel2<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten1 msel1<1:0> fsel1<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten0 msel0<1:0> fsel0<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten3: filter 3 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel3<1:0>: filter 3 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel3<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten2: filter 2 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel2<1:0>: filter 2 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel2<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 267 pic32mx5xx/6xx/7xx bit 15 flten1: filter 1 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel1<1:0>: filter 1 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel1<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten0: filter 0 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel0<1:0>: filter 0 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel0<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-10: cifltcon0: can filter control register 0 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 268 ? 2009-2013 microchip technology inc. register 23-11: cifltcon1: can filter control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten7 msel7<1:0> fsel7<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten6 msel6<1:0> fsel6<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten5 msel5<1:0> fsel5<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten4 msel4<1:0> fsel4<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten7: filter 7 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel7<1:0>: filter 7 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel7<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten6: filter 6 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel6<1:0>: filter 6 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel6<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 269 pic32mx5xx/6xx/7xx bit 15 flten5: filter 17 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel5<1:0>: filter 5 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel5<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten4: filter 4 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel4<1:0>: filter 4 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel4<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-11: cifltcon1: can filter control register 1 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 270 ? 2009-2013 microchip technology inc. register 23-12: cifltcon2: can filter control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten11 msel11<1:0> fsel11<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten10 msel10<1:0> fsel10<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten9 msel9<1:0> fsel9<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten8 msel8<1:0> fsel8<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten11: filter 11 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel11<1:0>: filter 11 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel11<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten10: filter 10 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel10<1:0>: filter 10 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel10<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 271 pic32mx5xx/6xx/7xx bit 15 flten9: filter 9 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel9<1:0>: filter 9 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel9<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten8: filter 8 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel8<1:0>: filter 8 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel8<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-12: cifltcon2: can filter control register 2 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 272 ? 2009-2013 microchip technology inc. register 23-13: cifltcon3: can filter control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten15 msel15<1:0> fsel15<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten14 msel14<1:0> fsel14<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten13 msel13<1:0> fsel13<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten12 msel12<1:0> fsel12<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten15: filter 15 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel15<1:0>: filter 15 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel15<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten14: filter 14 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel14<1:0>: filter 14 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel14<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 273 pic32mx5xx/6xx/7xx bit 15 flten13: filter 13 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel13<1:0>: filter 13 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel13<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten12: filter 12 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel12<1:0>: filter 12 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel12<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-13: cifltcon3: can filter control register 3 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 274 ? 2009-2013 microchip technology inc. ,4 register 23-14: cifltcon4: can filter control register 4 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten19 msel19<1:0> fsel19<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten18 msel18<1:0> fsel18<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten17 msel17<1:0> fsel17<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten16 msel16<1:0> fsel16<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten19: filter 19 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel19<1:0>: filter 19 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel19<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten18: filter 18 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel18<1:0>: filter 18 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel18<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 275 pic32mx5xx/6xx/7xx bit 15 flten17: filter 13 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel17<1:0>: filter 17 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel17<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten16: filter 16 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel16<1:0>: filter 16 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel16<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-14: cifltcon4: can filter control register 4 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 276 ? 2009-2013 microchip technology inc. register 23-15: cifltcon5: can filter control register 5 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten23 msel23<1:0> fsel23<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten22 msel22<1:0> fsel22<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten21 msel21<1:0> fsel21<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten20 msel20<1:0> fsel20<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten23: filter 23 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel23<1:0>: filter 23 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel23<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten22: filter 22 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel22<1:0>: filter 22 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel22<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 277 pic32mx5xx/6xx/7xx bit 15 flten21: filter 21 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel21<1:0>: filter 21 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel21<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten20: filter 20 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel20<1:0>: filter 20 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel20<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-15: cifltcon5: can filter control register 5 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 278 ? 2009-2013 microchip technology inc. register 23-16: cifltcon6: can filter control register 6 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten27 msel27<1:0> fsel27<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten26 msel26<1:0> fsel26<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten25 msel25<1:0> fsel25<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten24 msel24<1:0> fsel24<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten27: filter 27 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel27<1:0>: filter 27 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel27<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten26: filter 26 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel26<1:0>: filter 26 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel26<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 279 pic32mx5xx/6xx/7xx bit 15 flten25: filter 25 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel25<1:0>: filter 25 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel25<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten24: filter 24 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel24<1:0>: filter 24 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel24<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-16: cifltcon6: can filter control register 6 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 280 ? 2009-2013 microchip technology inc. register 23-17: cifltcon7: can filter control register 7 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten31 msel31<1:0> fsel31<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten30 msel30<1:0> fsel30<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten29 msel29<1:0> fsel29<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten28 msel28<1:0> fsel28<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 flten31: filter 31 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel31<1:0>: filter 31 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel31<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten30: filter 30enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel30<1:0>: filter 30mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel30<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 281 pic32mx5xx/6xx/7xx bit 15 flten29: filter 29 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel29<1:0>: filter 29 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel29<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten28: filter 28 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel28<1:0>: filter 28 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel28<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 ? ? ? 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 23-17: cifltcon7: can filter control register 7 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is ? 0 ?.
pic32mx5xx/6xx/7xx ds60001156h-page 282 ? 2009-2013 microchip technology inc. register 23-18: cirxfn: can acceptance fi lter ?n? register 7 (n = 0 through 31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid<10:3> 23:16 r/w-x r/w-x r/w-x u-0 r/w-0 u-0 r/w-x r/w-x sid<2:0> ?exid ? eid<17:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-21 sid<10:0>: standard identifier bits 1 = message address bit sidx must be ? 1 ? to match filter 0 = message address bit sidx must be ? 0 ? to match filter bit 20 unimplemented: read as ? 0 ? bit 19 exid: extended identifier enable bits 1 = match only messages with extended identifier addresses 0 = match only messages with standard identifier addresses bit 18 unimplemented: read as ? 0 ? bit 17-0 eid<17:0>: extended identifier bits 1 = message address bit eidx must be ? 1 ? to match filter 0 = message address bit eidx must be ? 0 ? to match filter note: this register can only be modified when the filter is disabled (fltenn = 0 ).
? 2009-2013 microchip technology inc. ds60001156h-page 283 pic32mx5xx/6xx/7xx register 23-19: cififoba: can message buffer base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 (1) r-0 (1) cififoba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 cififoba<31:0>: can fifo base address bits these bits define the base address of all message buf fers. individual message buffers are located based on the size of the previous message buffers. this add ress is a physical address. bits <1:0> are read-only and read as ? 0 ?, forcing the messages to be 32 -bit word-aligned in device ram. note 1: this bit is unimplemented and will always read ? 0 ?, which forces word-alignment of messages. note: this register can only be modified when the can module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100 ).
pic32mx5xx/6xx/7xx ds60001156h-page 284 ? 2009-2013 microchip technology inc. register 23-20: cififoconn: can fifo co ntrol register ?n? (n = 0 through 31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?fsize<4:0> (1) 15:8 u-0 s/hc-0 s/hc-0 r/w-0 u-0 u-0 u-0 u-0 ? freset uinc donly (1) ? ? ? ? 7:0 r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txen txabat (2) txlarb (3) txerr (3) txreq rtren txpr<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-21 unimplemented: read as ? 0 ? bit 20-16 fsize<4:0>: fifo size bits (1) 11111 = fifo is 32 messages deep ? ? ? 00010 = fifo is 3 messages deep 00001 = fifo is 2 messages deep 00000 = fifo is 1 message deep bit 15 unimplemented: read as ? 0 ? bit 14 freset: fifo reset bits 1 = fifo will be reset when bit is set, cleared by hardware when fifo is reset. after setting, the user should poll whether this bit is clear before taking any action. 0 = no effect bit 13 uinc: increment head/tail bit txen = 1 : (fifo configured as a transmit fifo) when this bit is set the fifo head will increment by a single message txen = 0 : (fifo configured as a receive fifo) when this bit is set the fifo tail will increment by a single message bit 12 donly: store message data only bit (1) txen = 1 : (fifo configured as a transmit fifo) this bit is not used and has no effect. txen = 0 : (fifo configured as a receive fifo) 1 = only data bytes will be stored in the fifo 0 = full message is stored, including identifier bit 11-8 unimplemented: read as ? 0 ? bit 7 txen: tx/rx buffer selection bit 1 = fifo is a transmit fifo 0 = fifo is a receive fifo note 1: these bits can only be modified when the can module is in configuration mode (opmod<2:0> bits (cicon<23:21>) = 100 ). 2: this bit is updated when a message completes (or aborts) or when the fifo is reset. 3: this bit is reset on any read of this register or when the fifo is reset.
? 2009-2013 microchip technology inc. ds60001156h-page 285 pic32mx5xx/6xx/7xx bit 6 txabat: message aborted bit (2) 1 = message was aborted 0 = message comple ted successfully bit 5 txlarb: message lost arbitration bit (3) 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerr: error detected during transmission bit (3) 1 = a bus error occured while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreq: message send request txen = 1 : (fifo configured as a transmit fifo) setting this bit to ? 1 ? requests sending a message. the bit will automatically clear when all the me ssages queued in the fifo are successfully sent. clearing the bit to ? 0 ? while set (? 1 ?) will request a message abort. txen = 0 : (fifo configured as a receive fifo) this bit has no effect. bit 2 rtren: auto rtr enable bit 1 = when a remote transmit is received, txreq will be set 0 = when a remote transmit is received, txreq will be unaffected bit 1-0 txpr<1:0>: message transmit priority bits 11 = highest message priority 10 = high intermediate message priority 01 = low intermediate message priority 00 = lowest message priority register 23-20: cififoconn: can fifo cont rol register ?n? (n = 0 through 31) note 1: these bits can only be modified when the can module is in configuration mode (opmod<2:0> bits (cicon<23:21>) = 100 ). 2: this bit is updated when a message completes (or aborts) or when the fifo is reset. 3: this bit is reset on any read of this register or when the fifo is reset.
pic32mx5xx/6xx/7xx ds60001156h-page 286 ? 2009-2013 microchip technology inc. register 23-21: cififointn: can fifo in terrupt register ?n? (n = 0 through 31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? txnfullie txhalfie txemptyie 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? rxovflie rxfullie r xhalfie rxnemptyie 15:8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? txnfullif (1) txhalfif txemptyif (1) 7:0 u-0 u-0 u-0 u-0 r/w-0 r-0 r-0 r-0 ? ? ? ? rxovflif rxfullif (1) rxhalfif (1) rxnemptyif (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as ? 0 ? bit 26 txnfullie: transmit fifo not full interrupt enable bit 1 = interrupt enabled for fifo not full 0 = interrupt disabled for fifo not full bit 25 txhalfie: transmit fifo half full interrupt enable bit 1 = interrupt enabled for fifo half full 0 = interrupt disabled for fifo half full bit 24 txemptyie: transmit fifo empty interrupt enable bit 1 = interrupt enabled for fifo empty 0 = interrupt disabled for fifo empty bit 23-20 unimplemented: read as ? 0 ? bit 19 rxovflie: overflow interrupt enable bit 1 = interrupt enabled for overflow event 0 = interrupt disabled for overflow event bit 18 rxfullie: full interrupt enable bit 1 = interrupt enabled for fifo full 0 = interrupt disabled for fifo full bit 17 rxhalfie: fifo half full interrupt enable bit 1 = interrupt enabled for fifo half full 0 = interrupt disabled for fifo half full bit 16 rxnemptyie: empty interrupt enable bit 1 = interrupt enabled for fifo not empty 0 = interrupt disabled for fifo not empty bit 15-11 unimplemented: read as ? 0 ? bit 10 txnfullif: transmit fifo not fu ll interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is not full 0 = fifo is full txen = 0 : (fifo configured as a receive buffer) unused, reads ? 0 ? note 1: this bit is read-only and refl ects the status of the fifo.
? 2009-2013 microchip technology inc. ds60001156h-page 287 pic32mx5xx/6xx/7xx bit 9 txhalfif: fifo transmit fifo half empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is ? half full 0 = fifo is > half full txen = 0 : (fifo configured as a receive buffer) unused, reads ? 0 ? bit 8 txemptyif: transmit fifo empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is empty 0 = fifo is not empty, at least 1 message queued to be transmitted txen = 0 : (fifo configured as a receive buffer) unused, reads ? 0 ? bit 7-4 unimplemented: read as ? 0 ? bit 3 rxovflif: receive fifo overflow interrupt flag bit txen = 1 : (fifo configured as a transmit buffer) unused, reads ? 0 ? txen = 0 : (fifo configured as a receive buffer) 1 = overflow event has occurred 0 = no overflow event occured bit 2 rxfullif: receive fifo full interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads ? 0 ? txen = 0 : (fifo configured as a receive buffer) 1 = fifo is full 0 = fifo is not full bit 1 rxhalfif: receive fifo half full interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads ? 0 ? txen = 0 : (fifo configured as a receive buffer) 1 = fifo is ?? half full 0 = fifo is < half full bit 0 rxnemptyif: receive buffer not empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads ? 0 ? txen = 0 : (fifo configured as a receive buffer) 1 = fifo is not empty, has at least 1 message 0 = fifo is empty register 23-21: cififointn: can fifo inte rrupt register ?n? (n = 0 through 31) note 1: this bit is read-only and refl ects the status of the fifo.
pic32mx5xx/6xx/7xx ds60001156h-page 288 ? 2009-2013 microchip technology inc. register 23-22: cififouan: ca n fifo user address register ?n? (n = 0 through 31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<31:24> 23:16 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<23:16> 15:8 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<15:8> 7:0 r-x r-x r-x r-x r-x r-x r-0 (1) r-0 (1) cififouan<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 cififouan<31:0>: can fifo user address bits txen = 1 : (fifo configured as a transmit buffer) a read of this register will return the address wh ere the next message is to be written (fifo head). txen = 0 : (fifo configured as a receive buffer) a read of this register will return the address where the next message is to be read (fifo tail). note 1: this bit will always read ? 0 ?, which forces byte-alignment of messages. note: this register is not guaranteed to read correctly in configuration mode, and s hould only be accessed when the module is not in configuration mode. register 23-23: cififocin: can module message index register ?n? (n = 0 through 31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 23:16 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 15:8 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 7:0 u-0u-0u-0r-0r-0r-0r-0r-0 ? ? ? cififoci<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-5 unimplemented: read as ? 0 ? bit 4-0 cififocin<4:0>: can side fifo message index bits txen = 1 : (fifo configured as a transmit buffer) a read of this register will return an index to the message that the fifo will ne xt attempt to transmit. txen = 0 : (fifo configured as a receive buffer) a read of this register will return an index to the message that the fifo will use to save the next message.
? 2009-2013 microchip technology inc. ds60001156h-page 289 pic32mx5xx/6xx/7xx 24.0 ethernet controller the ethernet controller is a bus master module that interfaces with an off-chip physical layer (phy) to implement a comple te ethernet node in a system. key features of the ether net controller include: ? supports 10/100 mbps data transfer rates ? supports full-duplex and half-duplex operation ? supports rmii and mii phy interface ? supports miim phy management interface ? supports both manual and automatic flow control ? ram descriptor-based dma operation for both receive and transmit path ? fully configurable interrupts ? configurable receive packet filtering - crc check - 64-byte pattern match - broadcast, multicast and unicast packets - magic packet? - 64-bit hash table - runt packet ? supports packet paylo ad checksum calculation ? supports various hardwa re statistics counters figure 24-1 illustrates a block diagram of the ethernet controller. figure 24-1: ethernet co ntroller block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 35. ?ethernet controller? (ds60001155) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. tx bus master system bus rx bus master tx dma tx flow control host if rx dma rx filter checksum mac external phy mii/rmii if miim if mac control and configuration registers tx function rx function dma control registers fast peripheral bus ethernet controller rx flow control ethernet dma rx bm tx bm tx fifo rx fifo
pic32mx5xx/6xx/7xx ds60001156h-page 290 ? 2009-2013 microchip technology inc. table 24-1 , table 24-2 , table 24-3 and ta b l e 2 4 - 4 show four interfaces and the associated pins that can be used with the ethernet controller. table 24-1: mii mode default interface signals (fmiien = 1 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxclk transmit clock etxen transmit enable etxd0 transmit data etxd1 transmit data etxd2 transmit data etxd3 transmit data etxerr transmit error erxclk receive clock erxdv receive data valid erxd0 receive data erxd1 receive data erxd2 receive data erxd3 receive data erxerr receive error ecrs carrier sense ecol collision indication table 24-2: rmii mode default interface signals (fmiien = 0 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxen transmit enable etxd0 transmit data etxd1 transmit data erefclk reference clock ecrsdv carrier sense ? receive data valid erxd0 receive data erxd1 receive data erxerr receive error note: ethernet controller pins that are not used by selected interface can be used by other peripherals. table 24-3: mii mode alternate interface signals (fmiien = 1 , fethio = 0 ) pin name description aemdc management clock aemdio management i/o aetxclk transmit clock aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aetxd2 transmit data aetxd3 transmit data aetxerr transmit error aerxclk receive clock aerxdv receive data valid aerxd0 receive data aerxd1 receive data aerxd2 receive data aerxd3 receive data aerxerr receive error aecrs carrier sense aecol collision indication note: the mii mode alternate interface is not available on 64-pin devices. table 24-4: rmii mode alternate interface signals (fmiien = 0 , fethio = 0 ) pin name description aemdc management clock aemdio management i/o aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aerefclk reference clock aecrsdv carrier sense ? receive data valid aerxd0 receive data aerxd1 receive data aerxerr receive error
? 2009-2013 microchip technology inc. ds60001156h-page 291 pic32mx5xx/6xx/7xx 24.1 control registers register 24-1: ethcon1: ethernet controller control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptv<15:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptv<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on ?sidl ? ? ? txrts rxen (1) 7:0 r/w-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 autofc ? ?manfc ? ? ? bufcdec legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 ptv<15:0>: pause timer value bits pause timer value used for flow control. this register should only be written when rxen (ethcon1<8>) is not set. these bits are only used for flow control operations. bit 15 on: ethernet on bit 1 = ethernet module is enabled 0 = ethernet module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: ethernet stop in idle mode bit 1 = ethernet module transfers are paused during idle mode 0 = ethernet module transfers continue during idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9 txrts: transmit request to send bit 1 = activate the tx logic and send the packet(s) defined in the tx edt 0 = stop transmit (when cleared by software) or transmit done (when cleared by hardware) after the bit is written with a ? 1 ?, it will clear to a ? 0 ? whenever the transmit logic has finished transmitting the requested packets in the ethernet descriptor table (edt). if a ? 0 ? is written by the cpu, the transmit logic finishes the current packet?s tr ansmission and then stops any further. this bit only affects tx operations. bit 8 rxen: receive enable bit (1) 1 = enable rx logic, packets are received and stored in the rx buffer as controlled by the filter configuration 0 = disable rx logic, no packets are received in the rx buffer this bit only affects rx operations. note 1: it is not recommended to clear the rxen bit and then make changes to any rx related field/register. the ethernet controller must be reinitialized (on cleared to ? 0 ?), and then the rx changes applied.
pic32mx5xx/6xx/7xx ds60001156h-page 292 ? 2009-2013 microchip technology inc. bit 7 autofc: automatic flow control bit 1 = automatic flow control is enabled 0 = automatic flow control is disabled setting this bit will enable automatic flow control. if set, the full and empty watermarks are used to automatically enable and disable the flow control, respectively. when the number of received buffers bufcnt (ethstat<16:23>) rises to the full wate rmark, flow control is automatically enabled. when the bufcnt falls to the empty watermark, flow control is automatically disabled. this bit is only used for flow control operations and affects both tx and rx operations. bit 6-5 unimplemented: read as ? 0 ? bit 4 manfc: manual flow control bit 1 = manual flow control is enabled 0 = manual flow control is disabled setting this bit will enable manual flow control. if set, the flow control logic will send a pause frame using the pause timer value in the ptv register. it will then resend a pause frame every 128 * ptv<15:0>/2 tx clock cycles until the bit is cleared. note: for 10 mbps operation, tx clock runs at 2.5 mhz. for 100 mbps operation, tx clock runs at 25 mhz. when this bit is cleared, the flow control logic will automatically send a pause frame with a 0x0000 pause timer value to disable flow control. this bit is only used for flow control operations and affects both tx and rx operations. bit 3-1 unimplemented: read as ? 0 ? bit 0 bufcdec: descriptor buffer count decrement bit the bufcdec bit is a write-1 bit that reads as ? 0 ?. when written with a ? 1 ?, the descriptor buffer counter, bufcnt, will decrement by one. if bu fcnt is incremented by the rx logic at the same time that this bit is written, the bufcnt value will remain unchanged. writing a ? 0 ? will have no effect. this bit is only used for rx operations. register 24-1: ethcon1: ethernet contro ller control register 1 (continued) note 1: it is not recommended to clear the rxen bit and then make changes to any rx related field/register. the ethernet controller must be re initialized (on cleared to ? 0 ?), and then the rx changes applied.
? 2009-2013 microchip technology inc. ds60001156h-page 293 pic32mx5xx/6xx/7xx register 24-2: ethcon2: ethernet controller control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ?rxbufsz<6:4> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 rxbufsz<3:0> ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as ? 0 ? bit 10-4 rxbufsz<6:0>: rx data buffer size for all rx descriptors (in 16-byte increments) bits 1111111 = rx data buffer size fo r descriptors is 2032 bytes ? ? ? 1100000 = rx data buffer size fo r descriptors is 1536 bytes ? ? ? 0000011 = rx data buffer size fo r descriptors is 48 bytes 0000010 = rx data buffer size fo r descriptors is 32 bytes 0000001 = rx data buffer size fo r descriptors is 16 bytes 0000000 = reserved bit 3-0 unimplemented: read as ? 0 ? note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 294 ? 2009-2013 microchip technology inc. register 24-3: ethtxst: ethernet cont roller tx packet descriptor start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 txstaddr<7:2> ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-2 txstaddr<31:2>: starting address of first transmit descriptor bits this register should not be written while any tr ansmit, receive or dma operations are in progress. this address must be 4-byte aligned (bits 1-0 must be ? 00 ?). bit 1-0 unimplemented: read as ? 0 ? note 1: this register is only used for tx operations. 2: this register will be updated by hardware with the la st descriptor used by the last successfully transmitted packet. register 24-4: ethrxst: ethernet controller rx packet descriptor start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 rxstaddr<7:2> ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-2 rxstaddr<31:2>: starting address of first receive descriptor bits this register should not be written while any tr ansmit, receive or dma operations are in progress. this address must be 4-byte aligned (bits 1-0 must be ? 00 ?). bit 1-0 unimplemented: read as ? 0 ? note 1: this register is only used for rx operations. 2: this register will be updated by hardware with the la st descriptor used by the last successfully transmitted packet.
? 2009-2013 microchip technology inc. ds60001156h-page 295 pic32mx5xx/6xx/7xx register 24-5: ethht0: ethernet controller hash table 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 ht<31:0>: hash table bytes 0-3 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the hten bit (ethrxfc<15>) = 0 . register 24-6: ethht1: ethernet controller hash table 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<63:56> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<55:48> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<47:40> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<39:32> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 ht<63:32>: hash table bytes 4-7 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the hten bit (ethrxfc<15>) = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 296 ? 2009-2013 microchip technology inc. register 24-7: ethpmm0: ethernet cont roller pattern match mask 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 pmm<31:24>: pattern match mask 3 bits bit 23-16 pmm<23:16>: pattern match mask 2 bits bit 15-8 pmm<15:8>: pattern match mask 1 bits bit 7-0 pmm<7:0>: pattern match mask 0 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 . register 24-8: ethpmm1: ethernet cont roller pattern match mask 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<63:56> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<55:48> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<47:40> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<39:32> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 pmm<63:56>: pattern match mask 7 bits bit 23-16 pmm<55:48>: pattern match mask 6 bits bit 15-8 pmm<47:40>: pattern match mask 5 bits bit 7-0 pmm<39:32>: pattern match mask 4 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 .
? 2009-2013 microchip technology inc. ds60001156h-page 297 pic32mx5xx/6xx/7xx register 24-9: ethpmcs: ethernet controller pattern match checksum register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmcs<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmcs<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-8 pmcs<15:8>: pattern match checksum 1 bits bit 7-0 pmcs<7:0>: pattern match checksum 0 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 . register 24-10: ethpmo: ethernet cont roller pattern match offset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmo<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmo<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 pmo<15:0>: pattern match offset 1 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 298 ? 2009-2013 microchip technology inc. register 24-11: ethrxfc: ethernet cont roller receive filter configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hten mpen ? notpm pmmode<3:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 crcerren crcoken runterren runten ucen notmeen mcen bcen legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 hten: enable hash table filtering bit 1 = enable hash table filtering 0 = disable hash table filtering bit 14 mpen: magic packet? enable bit 1 = enable magic packet filtering 0 = disable magic packet filtering bit 13 unimplemented: read as ? 0 ? bit 12 notpm: pattern match inversion bit 1 = the pattern match checksum must not matc h for a successful pa ttern match to occur 0 = the pattern match checksu m must match for a successful pattern match to occur this bit determines whether pattern match checksum must match in order for a succe ssful pattern match to occur. bit 11-8 pmmode<3:0>: pattern match mode bits 1001 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (packet = magic packet) (1,3) 1000 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (hash table filter match) (1,2) 0111 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = broadcast address) (1) 0110 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = broadcast address) (1) 0101 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = unicast address) (1) 0100 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = unicast address) (1) 0011 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = station address) (1) 0010 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and (destination address = station address) (1) 0001 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) (1) 0000 = pattern match is disabled; pattern match is always unsuccessful note 1: xor = true when either one or the other conditions are true, but not both. 2: this hash table filter match is active regardless of the value of the hten bit. 3: this magic packet filter match is active regardless of the value of the mpen bit. note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
? 2009-2013 microchip technology inc. ds60001156h-page 299 pic32mx5xx/6xx/7xx bit 7 crcerren: crc error collection enable bit 1 = the received packet crc must be invalid for the packet to be accepted 0 = disable crc error collection filtering this bit allows the user to collect all packets that have an invalid crc. bit 6 crcoken: crc ok enable bit 1 = the received packet crc must be valid for the packet to be accepted 0 = disable crc filtering this bit allows the user to reject all packets that have an invalid crc. bit 5 runterren: runt error collection enable bit 1 = the received packet must be a runt packet for the packet to be accepted 0 = disable runt error collection filtering this bit allows the user to collect all packets that are runt packets. for this filter, a runt packet is defined as any packet with a size of less than 64 bytes (when crcoken = 0 ) or any packet with a size of less than 64 bytes that has a valid crc (when crcoken = 1 ). bit 4 runten: runt enable bit 1 = the received packet must not be a runt packet for the packet to be accepted 0 = disable runt filtering this bit allows the user to reject all runt packets. fo r this filter, a runt packet is defined as any packet with a size of less than 64 bytes. bit 3 ucen: unicast enable bit 1 = enable unicast filtering 0 = disable unicast filtering this bit allows the user to accept all unicast pa ckets whose destination address matches the station address. bit 2 notmeen: not me unicast enable bit 1 = enable not me unicast filtering 0 = disable not me unicast filtering this bit allows the user to accept all unicast packe ts whose destination address does not match the station address. bit 1 mcen: multicast enable bit 1 = enable multicast filtering 0 = disable multicast filtering this bit allows the user to accept all multicast address packets. bit 0 bcen: broadcast enable bit 1 = enable broadcast filtering 0 = disable broadcast filtering this bit allows the user to accept all broadcast address packets. register 24-11: ethrxfc: ethernet cont roller receive filter configuration register (continued) note 1: xor = true when either one or the other conditions are true, but not both. 2: this hash table filter match is active regardless of the value of the hten bit. 3: this magic packet filter match is active regardless of the value of the mpen bit. note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 300 ? 2009-2013 microchip technology inc. register 24-12: ethrxwm: ethernet co ntroller receive watermarks register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxfwm<7:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxewm<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-16 rxfwm<7:0>: receive full watermark bits the software controlled rx buffer full watermark pointer is compared against the rx bufcnt to determine the full watermark condition for the fw mark interrupt and for enabling flow control when automatic flow control is enabled. the full waterma rk pointer should always be greater than the empty watermark pointer. bit 15-8 unimplemented: read as ? 0 ? bit 7-0 rxewm<7:0>: receive empty watermark bits the software controlled rx buffer empty watermark pointer is compared against the rx bufcnt to determine the empty watermark condition for the ewma rk interrupt and for disabling flow control when automatic flow control is enabled. the empty wate rmark pointer should always be less than the full watermark pointer. note: this register is only used for rx operations.
? 2009-2013 microchip technology inc. ds60001156h-page 301 pic32mx5xx/6xx/7xx register 24-13: ethien: ethernet controller interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 ? txbuseie (1) rxbuseie (2) ? ? ? ewmarkie (2) fwmarkie (2) 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rxdoneie (2) pktpendie (2) rxactie (2) ? txdoneie (1) txabortie (1) rxbufnaie (2) rxovflwie (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 txbuseie: transmit bvci bus erro r interrupt enable bit (1) 1 = enable txbus error interrupt 0 = disable txbus error interrupt bit 13 rxbuseie: receive bvci bus erro r interrupt enable bit (2) 1 = enable rxbus error interrupt 0 = disable rxbus error interrupt bit 12-10 unimplemented: read as ? 0 ? bit 9 ewmarkie: empty watermark interrupt enable bit (2) 1 = enable ewmark interrupt 0 = disable ewmark interrupt bit 8 fwmarkie: full watermark interrupt enable bit (2) 1 = enable fwmark interrupt 0 = disable fwmark interrupt bit 7 rxdoneie: receiver done interrupt enable bit (2) 1 = enable rxdone interrupt 0 = disable rxdone interrupt bit 6 pktpendie: packet pending interrupt enable bit (2) 1 = enable pktpend interrupt 0 = disable pktpend interrupt bit 5 rxactie: rx activity interrupt enable bit 1 = enable r xact interrupt 0 = disable rxact interrupt bit 4 unimplemented: read as ? 0 ? bit 3 txdoneie: transmitter done interrupt enable bit (1) 1 = enable txdone interrupt 0 = disable txdone interrupt bit 2 txabortie: transmitter abort interrupt enable bit (1) 1 = enable txabort interrupt 0 = disable txabort interrupt bit 1 rxbufnaie: receive buffer not available interrupt enable bit (2) 1 = enable rxbufna interrupt 0 = disable rxbufna interrupt bit 0 rxovflwie: receive fifo overflow interrupt enable bit (2) 1 = enable rxovflw interrupt 0 = disable rxovflw interrupt note 1: this bit is only used for tx operations. 2: this bit is only used for rx operations.
pic32mx5xx/6xx/7xx ds60001156h-page 302 ? 2009-2013 microchip technology inc. register 24-14: ethirq: ethernet co ntroller interrupt request register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 ? txbuse rxbuse ? ? ?ewmarkfwmark 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rxdone pktpend rxact ? txdone txabort rxbufna rxovflw legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 txbuse: transmit bvci bus error interrupt bit 1 = bvci bus error has occurred 0 = bvci bus error has not occurred this bit is set when the tx dma encounters a bvci bus error during a memory access. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. bit 13 rxbuse: receive bvci bus error interrupt bit 1 = bvci bus error has occurred 0 = bvci bus error has not occurred this bit is set when the rx dma encounters a bvci bus error during a memory access. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. bit 12-10 unimplemented: read as ? 0 ? bit 9 ewmark: empty watermark interrupt bit 1 = empty watermark pointer reached 0 = no interrupt pending this bit is set when the rx descriptor buffer count is less than or equal to the value in the rxewm bit (ethrxwm<0:7>) value. it is cleared by bufcnt bit (ethstat<16:23>) being incremented by hardware. writing a ? 0 ? or a ? 1 ? has no effect. bit 8 fwmark: full watermark interrupt bit 1 = full watermark pointer reached 0 = no interrupt pending this bit is set when the rx descriptor buffer count is greater than or equal to the value in the rxfwm bit (ethrxwm<16:23>) field. it is cleared by writing the bufcdec (ethcon1<0>) bit to decrement the bufcnt counter. writing a ? 0 ? or a ? 1 ? has no effect. bit 7 rxdone: receive done interrupt bit 1 = rx packet was successfully received 0 = no interrupt pending this bit is set whenever an rx packet is successfully received. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. note: it is recommended to use the set, clr, or inv register s to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2009-2013 microchip technology inc. ds60001156h-page 303 pic32mx5xx/6xx/7xx bit 6 pktpend: packet pending interrupt bit 1 = rx packet pending in memory 0 = rx packet is not pending in memory this bit is set when the bufcnt counter has a value other than ? 0 ?. it is cleared by either a reset or by writing the bufcdec bit to decrement the bufcnt counter. writing a ? 0 ? or a ? 1 ? has no effect. bit 5 rxact: receive activity interrupt bit 1 = rx packet data was successfully received 0 = no interrupt pending this bit is set whenever rx packet data is stored in the rxbm fifo. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. bit 4 unimplemented: read as ? 0 ? bit 3 txdone: transmit done interrupt bit 1 = tx packet was successfully sent 0 = no interrupt pending this bit is set when the currently transmitted tx pa cket completes transmission, and the transmit status vector is loaded into the first descriptor used for the packet. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. bit 2 txabort: transmit abort condition interrupt bit 1 = tx abort condition occurred on the last tx packet 0 = no interrupt pending this bit is set when the mac aborts the transmissi on of a tx packet for one of the following reasons: ? jumbo tx packet abort ? underrun abort ? excessive defer abort ? late collision abort ? excessive collisions abort this bit is cleared by either a reset or cpu write of a ? 1 ? to the clr register. bit 1 rxbufna: receive buffer not available interrupt bit 1 = rx buffer descriptor not available condition has occurred 0 = no interrupt pending this bit is set by a rx buffer descriptor overrun condit ion. it is cleared by eit her a reset or a cpu write of a ? 1 ? to the clr register. bit 0 rxovflw: receive fifo over flow error bit 1 = rx fifo overflow error condition has occurred 0 = no interrupt pending rxovflw is set by the rxbm logic for an rx fifo ov erflow condition. it is cleared by either a reset or cpu write of a ? 1 ? to the clr register. register 24-14: ethirq: ethernet co ntroller interrupt request register note: it is recommended to use the set, clr, or inv register s to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mx5xx/6xx/7xx ds60001156h-page 304 ? 2009-2013 microchip technology inc. register 24-15: ethstat: ethernet controller status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufcnt<7:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ethbusy (1) txbusy (2) rxbusy (2) ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-16 bufcnt<7:0>: packet buffer count bits number of packet buffers received in memory. once a packet has been successfully received, this register is incremented by hardware based on the number of descriptors used by the packet. software decrements the counter (by writing to the bufcdec bit (ethcon1<0>) for each descriptor used) after a packet has been read out of the buffer. the register does not roll over (0xff to 0x00) when hardware tries to increment the register and the register is alread y at 0xff. conversely, the register does not roll under (0x00 to 0xff) when software tries to decrement the register and the register is already at 0x 0000. when software attempts to decrement the counter at the same time that the ha rdware attempts to increm ent the counter, the counter value will remain unchanged. when this register value reaches 0xff, the rx logi c will halt (only if automatic flow control is enabled) awaiting software to write the bufcdec bit in order to decrement the register below 0xff. if automatic flow control is disabled, the rxdma will continue processing and th e bufcnt will saturate at a value of 0xff. when this register is non-zero, the pktpend stat us bit will be set and an interrupt may be generated, depending on the value of the ethien bit register. when the ethrxst register is written, the bufcnt counter is automatically cleared to 0x00. note: bufcnt will not be cleared when on is set to ? 0 ?. this enables software to continue to utilize and decrement this count. bit 15-8 unimplemented: read as ? 0 ? bit 7 ethbusy: ethernet module busy bit (1) 1 = ethernet logic has been turned on (on (ethcon1<15>) = 1 ) or is completing a transaction 0 = ethernet logic is idle this bit indicates that the module has been turned on or is completing a transaction after being turned off. bit 6 txbusy: transmit busy bit (2) 1 = tx logic is receiving data 0 = tx logic is idle this bit indicates that a packet is currently being transmitted. a change in this status bit is not necessarily reflected by the txdone interrupt, as tx packe ts may be aborted or rejected by the mac. note 1: this bit will be set when the on bit (ethcon1<15>) = 1 . 2: this bit will be cleared when the on bit (ethcon1<15>) = 0 .
? 2009-2013 microchip technology inc. ds60001156h-page 305 pic32mx5xx/6xx/7xx bit 5 rxbusy: receive busy bit (2) 1 = rx logic is receiving data 0 = rx logic is idle this bit indicates that a packet is currently being re ceived. a change in this status bit is not necessarily reflected by the rxdone interrupt, as rx packets may be aborted or rejected by the rx filter. bit 4-0 unimplemented: read as ? 0 ? register 24-15: ethstat: ethernet cont roller status register (continued) note 1: this bit will be set when the on bit (ethcon1<15>) = 1 . 2: this bit will be cleared when the on bit (ethcon1<15>) = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 306 ? 2009-2013 microchip technology inc. register 24-16: ethrxovflow: ethernet controller receive overflow statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxovflwcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxovflwcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 rxovflwcnt<15:0>: dropped receive frames count bits increment counter for frames accept ed by the rx filter and subsequently dropped due to internal receive error (rxfifo overrun). this event also sets the rxovflw bit (ethirq<0>) interrupt flag. note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2009-2013 microchip technology inc. ds60001156h-page 307 pic32mx5xx/6xx/7xx register 24-17: ethfrmtxok: ethernet controller frames transmitted ok statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmtxokcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmtxokcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 frmtxokcnt<15:0>: frame transmitted ok count bits increment counter for frames successfully transmitted. note 1: this register is only used for tx operations. 2: this register is autom atically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mx5xx/6xx/7xx ds60001156h-page 308 ? 2009-2013 microchip technology inc. register 24-18: ethscolfrm: ethernet controller single collision frames statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 scolfrmcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 scolfrmcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 scolfrmcnt<15:0>: single collision frame count bits increment count for frames that were successfully transmitted on the second try. note 1: this register is only used for tx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2009-2013 microchip technology inc. ds60001156h-page 309 pic32mx5xx/6xx/7xx register 24-19: ethmcolfrm: ethernet controller multiple collision frames statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mcolfrmcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mcolfrmcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 mcolfrmcnt<15:0>: multiple collision frame count bits increment count for frames that we re successfully transmit ted after there was more than one collision. note 1: this register is only used for tx operations. 2: this register is autom atically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mx5xx/6xx/7xx ds60001156h-page 310 ? 2009-2013 microchip technology inc. register 24-20: ethfrmrxok: ethernet controller frames received ok statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmrxokcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmrxokcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 frmrxokcnt<15:0>: frames received ok count bits increment count for frames received successfully by th e rx filter. this count will not be incremented if there is a frame check sequence (fcs) or alignment error. note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2009-2013 microchip technology inc. ds60001156h-page 311 pic32mx5xx/6xx/7xx register 24-21: ethfcserr: ethernet controller frame check sequence error statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fcserrcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fcserrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 fcserrcnt<15:0>: fcs error count bits increment count for frames received with fcs error and th e frame length in bits is an integral multiple of 8bits. note 1: this register is only used for rx operations. 2: this register is autom atically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should be only done for debug/test purposes.
pic32mx5xx/6xx/7xx ds60001156h-page 312 ? 2009-2013 microchip technology inc. register 24-22: ethalgnerr: ethernet controller alignment errors statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 algnerrcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 algnerrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 algnerrcnt<15:0>: alignment error count bits increment count for frames with alignment errors. note that an alignment error is a frame that has an fcs error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble) note 1: this register is only used for rx operations. 2: this register is automatically clea red by hardware after a read operation, unless the byte enables for bytes 0/1 are ? 0 ?. 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should be only done for debug/test purposes.
? 2009-2013 microchip technology inc. ds60001156h-page 313 pic32mx5xx/6xx/7xx register 24-23: emac1cfg1: ethernet co ntroller mac conf iguration 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-1 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 soft reset sim reset ? ? reset rmcs reset rfun reset tmcs reset tfun 7:0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 ? ? ? loopback tx pause rx pause passall rx enable legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 softreset: soft reset bit setting this bit will put the macmii in reset. its default value is ? 1 ?. bit 14 simreset: simulation reset bit setting this bit will cause a reset to the random number generator within the transmit function. bit 13-12 unimplemented: read as ? 0 ? bit 11 resetrmcs: reset mcs/rx bit setting this bit will put the mac control s ub-layer/receive domain logic in reset. bit 10 resetrfun: reset rx function bit setting this bit will put the mac receive function logic in reset. bit 9 resettmcs: reset mcs/tx bit setting this bit will put the mac contro l sub-layer/tx domain logic in reset. bit 8 resettfun: reset tx fu nction bit setting this bit will put the mac transmit function logic in reset. bit 7-5 unimplemented: read as ? 0 ? bit 4 loopback: mac loopback mode bit 1 = mac transmit interface is loop backed to the mac receive interface 0 = mac normal operation bit 3 txpause: mac tx flow control bit 1 = pause flow control frames are allowed to be transmitted 0 = pause flow control frames are blocked bit 2 rxpause: mac rx flow control bit 1 = the mac acts upon received pause flow control frames 0 = received pause flow control frames are ignored bit 1 passall: mac pass all receive frames bit 1 = the mac will accept all frames regardless of type (normal vs. control) 0 = the received control frames are ignored bit 0 rxenable: mac receive enable bit 1 = enable the mac receiving of frames 0 = disable the mac receiving of frames note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 314 ? 2009-2013 microchip technology inc. register 24-24: emac1cfg2: ethernet co ntroller mac conf iguration 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 25/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ? excess dfr bpnobk off nobk off ? ? longpre purepre 7:0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 auto pad (1,2) vlan pad (1,2) pad enable (1,3) crc enable delaycrc hugefrm lengthck fulldplx legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 excessder: excess defer bit 1 = the mac will defer to carrier indefinitely as per the standard 0 = the mac will abort when the excessive deferral limit is reached bit 13 bpnobkoff: backpressure/no backoff bit 1 = the mac after incidentally causing a collision duri ng backpressure will immediately retransmit without backoff reducing the chance of further collisions and ensuring transmit packets get sent 0 = the mac will not remove the backoff bit 12 nobkoff: no backoff bit 1 = following a collision, the mac will immediately re transmit rather than using the binary exponential back- off algorithm as specified in the standard 0 = following a collision, the mac will use the binary exponential backoff algorithm bit 11-10 unimplemented: read as ? 0 ? bit 9 longpre: long preamble enforcement bit 1 = the mac only allows receive packets which contain preamble fields less than 12 bytes in length 0 = the mac allows any length preamble as per the standard bit 8 purepre: pure preamble enforcement bit 1 = the mac will verify the content of the preamble to ensure it contains 0x55 and is error-free. a packet with errors in its preamble is discarded 0 = the mac does not perform any preamble checking bit 7 autopad: automatic detect pad enable bit (1,2) 1 = the mac will automatically detect the type of fram e, either tagged or untagged, by comparing the two octets following the source address with 0x8100 (vlan protocol id) and pad accordingly 0 = the mac does not perform automatic detection note 1: table 24-5 provides a description of the pad function bas ed on the configuration of this register. 2: this bit is ignored if the padenable bit is cleared. 3: this bit is used in conjunction with the autopad and vlanpad bits. note: both 16-bit and 32-bit accesses are allowed to these registers (including the se t, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware
? 2009-2013 microchip technology inc. ds60001156h-page 315 pic32mx5xx/6xx/7xx table 24-5: pad operation bit 6 vlanpad: vlan pad enable bit (1,2) 1 = the mac will pad all short frames to 64 bytes and append a valid crc 0 = the mac does not perform padding of short frames bit 5 padenable: pad/crc enable bit (1,3) 1 = the mac will pad all short frames 0 = the frames presented to the mac have a valid length bit 4 crcenable: crc enable1 bit 1 = the mac will append a crc to every frame whether p adding was required or not. must be set if the padenable bit is set. 0 = the frames presented to the mac have a valid crc bit 3 delaycrc: delayed crc bit this bit determines the number of bytes, if any, of proprietary header inform ation that exist on the front of the ieee 802.3 frames. 1 = four bytes of header (ignored by the crc function) 0 = no proprietary header bit 2 hugefrm: huge frame enable bit 1 = frames of any length are transmitted and received 0 = huge frames are not allowed for receive or transmit bit 1 lengthck: frame length checking bit 1 = both transmit and receive frame lengths are comp ared to the length/type field. if the length/type field represents a length then the check is performed. mismatches are reported on the transmit/receive statistics vector. 0 = length/type field check is not performed bit 0 fulldplx: full-duplex operation bit 1 = the mac operates in full-duplex mode 0 = the mac operates in half-duplex mode register 24-24: emac1cfg2: ethernet co ntroller mac conf iguration 2 register note 1: table 24-5 provides a description of the pad function bas ed on the configuration of this register. 2: this bit is ignored if the padenable bit is cleared. 3: this bit is used in conjunction with the autopad and vlanpad bits. note: both 16-bit and 32-bit accesses are allowed to these registers (including the se t, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware type autopad vlanpad padenable action any xx0 no pad, check crc any 001 pad to 60 bytes, append crc any x11 pad to 64 bytes, append crc any 101 if untagged: pad to 60 bytes, append crc if vlan tagged: pad to 64 bytes, append crc
pic32mx5xx/6xx/7xx ds60001156h-page 316 ? 2009-2013 microchip technology inc. register 24-25: emac1ipgt: ethernet controller mac back-to-back interpacket gap register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 ? b2bipktgp<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-7 unimplemented: read as ? 0 ? bit 6-0 b2bipktgp<6:0>: back-to-back interpacket gap bits this is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet, to the beginning of the next. in full-duplex mode, the register value should be the desired period in nibble times minus 3. in half-duplex mode, the register value should be the desired period in nibble times minus 6. in full-duplex the recommended setting is 0x15 (21d), which rep- resents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). in half-duplex mode, the rec- ommended setting is 0x12 (18d), which also represents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware.
? 2009-2013 microchip technology inc. ds60001156h-page 317 pic32mx5xx/6xx/7xx register 24-26: emac1ipgr: ethernet controller mac non-back-to-back interpacket gap register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 ? nb2bipktgp1<6:0> 7:0 u-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 ? nb2bipktgp2<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14-8 nb2bipktgp1<6:0>: non-back-to-back interpacket gap part 1 bits this is a programmable field representing the op tional carriersense window referenced in section 4.2.3.2.1 ?deference? of the ieee 80. 23 specification. if the carrier is detected during the timing of ipgr1, the mac defers to the carrier. if, however, the carrier comes after ipgr 1, the mac continues timing ipgr2 and transmits, knowingly causing a collision, thus ens uring fair access to the medium. its range of values is 0x0 to ipgr2. its recommend value is 0xc (12d). bit 7 unimplemented: read as ? 0 ? bit 6-0 nb2bipktgp2<6:0>: non-back-to-back interpacket gap part 2 bits this is a programmable field representing the non- back-to-back inter-packet-gap. its recommended value is 0x12 (18d), which represents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 318 ? 2009-2013 microchip technology inc. register 24-27: emac1clrt: ethernet co ntroller mac collision window/retry limit register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 ? ? cwindow<5:0> 7:0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? retx<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13-8 cwindow<5:0>: collision window bits this is a programmable field representing the slot ti me or collision window during which collisions occur in properly configured networks. since the collision window starts at the beginning of transmission, the pre- amble and sfd is included. its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window. bit 7-4 unimplemented: read as ? 0 ? bit 3-0 retx<3:0>: retransmission maximum bits this is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. th e standard specifies the maximum number of attempts (attemptlimit) to be 0xf (15d). its default is ?0xf?. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware.
? 2009-2013 microchip technology inc. ds60001156h-page 319 pic32mx5xx/6xx/7xx register 24-28: emac1maxf: ethernet co ntroller mac maximum frame length register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 macmaxf<15:8> (1) 7:0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 macmaxf<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 macmaxf<15:0>: maximum frame length bits (1) these bits reset to 0x05ee, which represents a maximum receive frame of 1518 octets. an untagged maximum size ethernet frame is 1518 octets. a tagged frame adds four octets for a total of 1522 octets. if a shorter/longer maximum length restricti on is desired, program this 16-bit field. note 1: if a proprietary header is allowed, this bit should be adjusted accordingly. for example, if 4-byte headers are prepended to frames, macmaxf could be set to 1527 octets. this would allow the maximum vlan tagged frame plus the 4-byte header. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 320 ? 2009-2013 microchip technology inc. register 24-29: emac1supp: ethernet controller mac phy support register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 ? ? ? ? resetrmii (1) ? ? speedrmii (1) 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as ? 0 ? bit 11 resetrmii: reset rmii logic bit (1) 1 = reset the mac rmii module 0 = normal operation. bit 10-9 unimplemented: read as ? 0 ? bit 8 speedrmii: rmii speed bit (1) this bit configures the reduced mii logic for the current operating speed. 1 = rmii is running at 100 mbps 0 = rmii is running at 10 mbps bit 7-0 unimplemented: read as ? 0 ? note 1: this bit is only used for the rmii module. note: both 16-bit and 32-bit accesses are allowed to these re gisters (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware.
? 2009-2013 microchip technology inc. ds60001156h-page 321 pic32mx5xx/6xx/7xx register 24-30: emac1test: ethernet controller mac test register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? testbp testpause (1) shrtqnta (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as ? 0 ? bit 2 testbp: test backpressure bit 1 = the mac will assert backpressure on the link. backpressure causes pr eamble to be transmitted, raising carrier sense. a transmit packet from the system will be sent during backpressure. 0 = normal operation bit 1 testpause: test pause bit (1) 1 = the mac control sub-layer will inhibit transmission s, just as if a pause receive control frame with a non-zero pause time pa rameter was received 0 = normal operation bit 0 shrtqnta: shortcut pause quanta bit (1) 1 = the mac reduces the effective pause quan ta from 64 byte-times to 1 byte-time 0 = normal operation note 1: this bit is only for testing purposes. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 322 ? 2009-2013 microchip technology inc. table 24-6: miim clock selection register 24-31: emac1mcfg: ethernet controller mac mii management configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 resetmgmt ? ? ? ? ? ? ? 7:0 u-0 u-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? clksel<3:0> (1) nopre scaninc legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 resetmgmt: test reset mii management bit 1 = reset the mii management module 0 = normal operation bit 14-6 unimplemented: read as ? 0 ? bit 5-2 clksel<3:0>: mii management clock select 1 bits (1) these bits are used by the clock divide logic in creating the mii management clock (mdc), which the ieee 802.3 specification defines to be no faster than 2. 5 mhz. some phys support clock rates up to 12.5 mhz. bit 1 nopre: suppress preamble bit 1 = the mii management will perform read/write cycles without the 32-bit preamble field. some phys support suppressed preamble 0 = normal read/write cycles are performed bit 0 scaninc: scan increment bit 1 = the mii management module will perform read cycl es across a range of phys. the read cycles will start from address 1 through the value set in emac1madr 0 = continuous reads of the same phy note 1: table 24-6 provides a description of the clock divider encoding. note: both 16-bit and 32-bit accesses are allowed to these r egisters (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware. miim clock select emac1mcfg<5:2> sysclk divided by 4 000x sysclk divided by 6 0010 sysclk divided by 8 0011 sysclk divided by 10 0100 sysclk divided by 14 0101 sysclk divided by 20 0110 sysclk divided by 28 0111 sysclk divided by 40 1000 undefined any other combination
? 2009-2013 microchip technology inc. ds60001156h-page 323 pic32mx5xx/6xx/7xx register 24-32: emac1mcmd: ethernet co ntroller mac mii m anagement command register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?scanread legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-2 unimplemented: read as ? 0 ? bit 1 scan: mii management scan mode bit 1 = the mii management modul e will perform read cycles continuously (for example, useful for monitoring the link fail) 0 = normal operation bit 0 read: mii management read command bit 1 = the mii management module will perform a single read cycle. the read data is returned in the emac1mrdd register 0 = the mii management module will perform a write cyc le. the write data is taken from the emac1mwtd register note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 324 ? 2009-2013 microchip technology inc. register 24-33: emac1madr: ethernet co ntroller mac mii management address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 ? ? ? phyaddr<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? regaddr<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as ? 0 ? bit 12-8 phyaddr<4:0>: mii management phy address bits this field represents the 5-bit phy address field of management cycles. up to 31 phys can be addressed (0 is reserved). bit 7-5 unimplemented: read as ? 0 ? bit 4-0 regaddr<4:0>: mii management register address bits this field represents the 5-bit register address field of management cycles. up to 32 registers can be accessed. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware.
? 2009-2013 microchip technology inc. ds60001156h-page 325 pic32mx5xx/6xx/7xx register 24-34: emac1mwtd: ethernet co ntroller mac mii management write data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mwtd<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mwtd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 mwtd<15:0>: mii management write data bits when written, a mii management writ e cycle is performed using the 16-bi t data and the pre-configured phy and register addresses from the emac1madr register. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware. register 24-35: emac1mrdd: ethernet controller mac mii management read data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mrdd<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mrdd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 mrdd<15:0>: mii management read data bits following a mii management read cycle, the 16-bit data can be read from this location. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware.
pic32mx5xx/6xx/7xx ds60001156h-page 326 ? 2009-2013 microchip technology inc. register 24-36: emac1mind: ethernet cont roller mac mii management indicators register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? linkfail notvalid scan miimbusy legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 linkfail: link fail bit when ? 1 ? is returned - indicates link fail has occurred. this bit reflects the value last read from the phy status register. bit 2 notvalid: mii management read data not valid bit when ? 1 ? is returned - indicates an mii management read cy cle has not completed and the read data is not yet valid. bit 1 scan: mii management scanning bit when ? 1 ? is returned - indicates a scan operation (continuous mii management read cycles) is in progress. bit 0 miimbusy: mii management busy bit when ? 1 ? is returned - indicates mii management module is currently performing an mii management read or write cycle. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware.
? 2009-2013 microchip technology inc. ds60001156h-page 327 pic32mx5xx/6xx/7xx register 24-37: emac1sa0: ethernet co ntroller mac station address 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr6<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr5<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-8 stnaddr6<7:0>: station address octet 6 bits these bits hold the sixth transmitted octet of the station address. bit 7-0 stnaddr5<7:0>: station address octet 5 bits these bits hold the fifth transmitted octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
pic32mx5xx/6xx/7xx ds60001156h-page 328 ? 2009-2013 microchip technology inc. register 24-38: emac1sa1: ethernet co ntroller mac station address 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr4<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr3<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-8 stnaddr4<7:0>: station address octet 4 bits these bits hold the fourth transm itted octet of the station address. bit 7-0 stnaddr3<7:0>: station address octet 3 bits these bits hold the third transmitt ed octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed a nd are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
? 2009-2013 microchip technology inc. ds60001156h-page 329 pic32mx5xx/6xx/7xx register 24-39: emac1sa2: ethernet co ntroller mac station address 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr2<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr1<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 reserved: maintain as ? 0 ?; ignore read bit 15-8 stnaddr2<7:0>: station address octet 2 bits these bits hold the second transmitted octet of the station address. bit 7-0 stnaddr1<7:0>: station address octet 1 bits these bits hold the most significant (first transmitted) octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). 8-bit accesses are not allowed and are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
pic32mx5xx/6xx/7xx ds60001156h-page 330 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 331 pic32mx5xx/6xx/7xx 25.0 comparator the comparator module cont ains two comparators that can be configured in a variety of ways. key features of the comp arator module include: ? selectable inputs available include: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference (iv ref ) - comparator voltage reference (cv ref ) ? outputs can be inverted ? selectable interrupt generation a block diagram of the comparator module is illustrated in figure 25-1 . figure 25-1: comparator module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?comparator? (ds60001110) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. c1 cv ref (2) c1in+ (1) c1in+ c1in- c1out cout (cm1con<8>) cref cch<1:0> cpol coe on c2in+ iv ref (2) c1out (cmstat<0>) c2 cv ref (2) c2in+ c2in+ c2in- c2out cout (cm2con<8>) cref cpol coe on c1in+ iv ref (2) c2out (cmstat<1>) comparator 2 comparator 1 cch<1:0> note 1: on devices with a usb module, and when the module is e nabled, this pin is controlled by the usb module, and therefore, is not available as a comparator input. 2: internally connected. see section 26.0 ?comparator voltage reference (cv ref )? .
pic32mx5xx/6xx/7xx ds60001156h-page 332 ? 2009-2013 microchip technology inc. 25.1 control registers register 25-1: cmxcon: comparator ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r-0 on (1) coe cpol (2) ? ? ? ?cout 7:0 r/w-1 r/w-1 u-0 r/w-0 u-0 u-0 r/w-1 r/w-1 evpol<1:0> ? cref ? ? cch<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator on bit (1) clearing this bit does not affect t he other bits in this register. 1 = module is enabled. setting this bit does not affect the other bits in this register 0 = module is disabled and does not consume current. bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output cxout pin 0 = comparator output is not driven on the output cxout pin bit 13 cpol: comparator output inversion bit (2) 1 = output is inverted 0 = output is not inverted bit 12-9 unimplemented: read as ? 0 ? bit 8 cout: comparator output bit 1 = output of the comparator is a ? 1 ? 0 = output of the comparator is a ? 0 ? bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 unimplemented: read as ? 0 ? bit 4 cref: comparator positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c x in+ pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator negative input select bits for comparator 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the c2in+ pin for c1 and c1in+ pin for c2 01 = comparator inverting input is connected to the c1in+ pin for c1 and c2in+ pin for c2 00 = comparator inverting input is connected to the c1in- pin for c1 and c2in- pin for c2 note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: setting this bit will invert the signal to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one se lected by evpol<1:0>.
? 2009-2013 microchip technology inc. ds60001156h-page 333 pic32mx5xx/6xx/7xx register 25-2: cmstat: comparator status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 ? ? ? ? ? ?c2outc1out legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = all comparator modules are disabled while in idle mode 0 = all comparator modules continue to operate while in idle mode bit 12-2 unimplemented: read as ? 0 ? bit 1 c2out: comparator output bit 1 = output of comparator 2 is a ? 1 ? 0 = output of comparator 2 is a ? 0 ? bit 0 c1out: comparator output bit 1 = output of comparator 1 is a ? 1 ? 0 = output of comparator 1 is a ? 0 ?
pic32mx5xx/6xx/7xx ds60001156h-page 334 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 335 pic32mx5xx/6xx/7xx 26.0 comparator voltage reference (cv ref ) the cv ref module is a 16-tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. a block diagram of the module is illustrated in figure 26-1 . the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. the module?s supply refer- ence can be provided from either device v dd /v ss or an external voltage reference. the cv ref output is avail- able for the comparators and typically available for pin output. key features of the cv ref module include: ? high and low range selection ? sixteen output levels available for each range ? internally connected to comparators to conserve device pins ? output can be connected to a pin figure 26-1: comparator voltage refe rence module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the inform ation in this data sheet, refer to section 20. ?comparator voltage reference (cv ref )? (ds60001109) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32) . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv refout av ss cvroe (cvrcon<6>) cv ref v refsel (1) iv ref 1.2v 0.6v bgsel<1:0> (1) cv rsrc note 1: this bit is not available on pic32mx575/675/695/775/795 devices. on these devices cv ref is generated by the register network and iv ref is connected to 0.6v.
pic32mx5xx/6xx/7xx ds60001156h-page 336 ? 2009-2013 microchip technology inc. 26.1 control register register 26-1: cvrcon: comparator voltage reference control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-1 on (1) ? ? ? ? vrefsel (2) bgsel<1:0> (2) 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cvroe cvrr cvrss cvr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator voltage reference on bit (1) setting or clearing this bit does not affe ct the other bits in this register. 1 = module is enabled 0 = module is disabled and does not consume current bit 14-11 unimplemented: read as ? 0 ? bit 10 vrefsel: voltage reference select bit (2) 1 =cv ref = v ref + 0 =cv ref is generated by the resistor network bit 9-8 bgsel<1:0>: band gap reference source bits (2) 11 =iv ref = v ref + 10 = reserved 01 =iv ref = 0.6v (nominal, default) 00 =iv ref = 1.2v (nominal) bit 7 unimplemented: read as ? 0 ? bit 6 cvroe: cv refout enable bit 1 = voltage level is output on cv refout pin 0 = voltage level is disconnected from cv refout pin bit 5 cvrr: cv ref range selection bit 1 = 0 to 0.67 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss: cv ref source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator voltage reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0>: cv ref value selection 0 ? cvr<3:0> ? 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref =1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc ) note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: these bits are not available on pic32mx575/675/775/7 95 devices. on these devi ces, the reset value for cvron is ? 0000 ?.
? 2009-2013 microchip technology inc. ds60001156h-page 337 pic32mx5xx/6xx/7xx 27.0 power-saving features this section describes power-saving features for the pic32mx5xx/6xx/7xx family of devices. these devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumpti on with device performance. in all of the methods and modes described in this section, power-saving is controlled by software. 27.1 power-saving with cpu running when the cpu is running, power consumption can be controlled by reducing t he cpu clock frequency, lowering the peripheral bus clock (pbclk) and by individually disabling modules. these methods are grouped into the following categories: ? frc run mode: the cpu is clocked from the frc clock source with or without postscalers. ? lprc run mode: the cpu is clocked from the lprc clock source. ?s osc run mode: the cpu is clocked from the s osc clock source. in addition, the peripheral bus scaling mode is available where peripherals are clocked at the programmable fraction of the cpu clock (sysclk). 27.2 cpu halted methods the device supports two power-saving modes, sleep and idle, both of which halt the clock to the cpu. these modes operate with all clock sources, as listed below: ? p osc idle mode: the system clock is derived from the p osc . the system clock source continues to operate. peripherals continue to operate, but can optionally be individually disabled. ? frc idle mode: the system clock is derived from the frc with or without postscalers. peripherals continue to operate, but can optionally be individually disabled. ? s osc idle mode: the system clock is derived from the s osc . peripherals continue to operate, but can optionally be individually disabled. ? lprc idle mode: the system clock is derived from the lprc. peripherals continue to operate, but can optionally be individually disabled. this is the lowest power mode for the device with a clock running. ? sleep mode: the cpu, the system clock source and any peripherals that operate from the system clock source are halted. some peripherals can operate in sleep using specific clock sources. this is the lowest power mode for the device. 27.3 power-saving operation peripherals and the cpu can be halted or disabled to further reduce power consumption. 27.3.1 sleep mode sleep mode has the lowest power consumption of the device power-saving operating modes. the cpu and most peripherals are halted. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: ? the cpu is halted ? the system clock source is typically shutdown. see section 27.3.3 ?peripheral bus scaling method? for specific information. ? there can be a wake-up delay based on the oscillator selection ? the fail-safe clock monitor (fscm) does not operate during sleep mode ? the bor circuit, if enabled, remains operative during sleep mode ? the wdt, if enabled, is not automatically cleared prior to entering sleep mode ? some peripherals can cont inue to operate at limited functionality in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart and peripherals that use an external clock input or the internal lprc oscillator (e.g., rtcc, timer1 and input capture). ? i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep ? modules can be individually disabled by software prior to entering sleep in order to further reduce consumption note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. ?power- saving features? (ds60001130) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information.
pic32mx5xx/6xx/7xx ds60001156h-page 338 ? 2009-2013 microchip technology inc. the processor will exit, or ?wake-up?, from sleep on one of the following events: ? on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. ? on any form of device reset ? on a wdt time-out if the interrupt priority is lower than or equal to the current priority, the cpu will remain halted, but the pbclk will start running and the device will enter into idle mode. 27.3.2 idle mode in idle mode, the cpu is halted but the system clock (sysclk) source is still enabled. this allows peripher- als to continue operation when the cpu is halted. peripherals can be individually configured to halt when entering idle by setting their respective sidl bit. latency, when exiting idle mode, is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen bit (osccon<4>) is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: ? on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of the cpu. if the priority of the interrupt event is lower than or equal to curre nt priority of the cpu, the cpu will remain halted and the device will remain in idle mode. ? on any form of device reset ? on a wdt time-out interrupt 27.3.3 peripheral bus scaling method most of the peripherals on the device are clocked using the pbclk. the peripheral bus (pb) can be scaled rel- ative to the sysclk to minimize the dynamic power consumed by the peripherals. the pbclk divisor is con- trolled by pbdiv<1:0> (osccon<20:19>), allowing sysclk to pbclk ratios of 1:1, 1:2, 1:4 and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as usb, interrupt control- ler, dma, bus matrix and prefetch cache are clocked directly from sysclk. as a result, they are not affected by pbclk divisor changes. changing the pbclk divisor affects: ? the cpu to peripheral access latency. the cpu has to wait for next pbclk edge for a read to complete. in 1:8 mode, this results in a latency of one to seven sysclks. ? the power consumption of the peripherals. power consumption is directly proportional to the fre- quency at which the peripherals are clocked. the greater the divisor, the lower the power consumed by the peripherals. to minimize dynamic power, the pb divisor should be chosen to run the peripherals at the lowest frequency that provides acceptabl e system performance. when selecting a pbclk divider, peripheral clock require- ments, such as baud rate accuracy, should be taken into account. for example, the uart peripheral may not be able to achieve all baud rate values at some pbclk divider depending on the sysclk value. note 1: changing the pbclk divider ratio requires recalculation of peripheral tim- ing. for example, assume the uart is configured for 9600 baud with a pb clock ratio of 1:1 and a p osc of 8 mhz. when the pb clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. for this reason, any timing cal- culation required for a peripheral should be performed with the new pb clock fre- quency instead of scaling the previous value based on a change in the pb divisor ratio. 2: oscillator start-up and pll lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the pll. for example, assume the clock source is switched from p osc to lprc just prior to entering sleep in order to save power. no oscillator start- up delay would be applied when exiting idle. however, when switching back to p osc , the appropriate pll and/or oscillator start-up/lock delays would be applied.
? 2009-2013 microchip technology inc. ds60001156h-page 339 pic32mx5xx/6xx/7xx 28.0 special features pic32mx5xx/6xx/7xx devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. key features include: ? flexible device configuration ? watchdog timer (wdt) ? joint test action group (jtag) interface ? in-circuit serial programming? (icsp?) 28.1 configuration bits the configuration bits can be programmed using the following registers to select various device configurations. ? devcfg0: device configuration word 0 ? devcfg1: device configuration word 1 ? devcfg2: device configuration word 2 ? devcfg3: device configuration word 3 ? devid: device and revision id register note: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?watchdog timer and power-up timer? (ds60001114), section 24. ?configuration? (ds60001124) and section 33. ?programming and diagnostics? (ds60001129) in the ?pic32 family reference manual? , which are available from the microchip web site ( www.microchip.com/pic32 ).
pic32mx5xx/6xx/7xx ds60001156h-page 340 ? 2009-2013 microchip technology inc. register 28-1: devcfg0: d evice configuration word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r/p r-1 r-1 r-1 r/p ? ? ?cp ? ? ?bwp 23:16 r-1 r-1 r-1 r-1 r/p r/p r/p r/p ? ? ? ?pwp<7:4> 15:8 r/p r/p r/p r/p r-1 r-1 r-1 r-1 pwp<3:0> ? ? ? ? 7:0 r-1 r-1 r-1 r-1 r/p r-1 r/p r/p ? ? ? ? icesel ? debug<1:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 reserved: write ? 0 ? bit 30-29 reserved: write ? 1 ? bit 28 cp: code-protect bit prevents boot and program flash me mory from being read or modified by an external programming device. 1 = protection is disabled 0 = protection is enabled bit 27-25 reserved: write ? 1 ? bit 24 bwp: boot flash write-protect bit prevents boot flash memory from bei ng modified during code execution. 1 = boot flash is writable 0 = boot flash is not writable bit 23-20 reserved: write ? 1 ? bit 19-12 pwp<7:0>: program flash write-protect bits prevents selected program flash memory pages from being modified during code execution. the pwp bits represent the 1?s complement of the number of write-protected program flash memory pages. 11111111 = disabled 11111110 = 0xbd00_0fff 11111101 = 0xbd00_1fff 11111100 = 0xbd00_2fff 11111011 = 0xbd00_3fff 11111010 = 0xbd00_4fff 11111001 = 0xbd00_5fff 11111000 = 0xbd00_6fff 11110111 = 0xbd00_7fff 11110110 = 0xbd00_8fff 11110101 = 0xbd00_9fff 11110100 = 0xbd00_afff 11110011 = 0xbd00_bfff 11110010 = 0xbd00_cfff 11110001 = 0xbd00_dfff 11110000 = 0xbd00_efff 11101111 = 0xbd00_ffff ? ? ? 01111111 = 0xbd07_ffff bit 11-4 reserved: write ? 1 ?
? 2009-2013 microchip technology inc. ds60001156h-page 341 pic32mx5xx/6xx/7xx bit 3 icesel: in-circuit emulator/debugger communication channel select bit 1 = pgec2/pged2 pair is used 0 = pgec1/pged1 pair is used bit 2 reserved: write ? 1 ? bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 11 = debugger is disabled 10 = debugger is enabled 01 = reserved (same as ? 11 ? setting) 00 = reserved (same as ? 11 ? setting) register 28-1: devcfg0: device configuration word 0 (continued)
pic32mx5xx/6xx/7xx ds60001156h-page 342 ? 2009-2013 microchip technology inc. register 28-2: devcfg1: d evice configuration word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r/p r-1 r-1 r/p r/p r/p r/p r/p fwdten ? ? wdtps<4:0> 15:8 r/p r/p r/p r/p r-1 r/p r/p r/p fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> 7:0 r/p r-1 r/p r-1 r-1 r/p r/p r/p ieso ? fsoscen ? ?fnosc<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 reserved: write ? 1 ? bit 23 fwdten: watchdog timer enable bit 1 = the wdt is enabled and cannot be disabled by software 0 = the wdt is not enabled; it can be enabled in software bit 22-21 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = 10100 bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source.
? 2009-2013 microchip technology inc. ds60001156h-page 343 pic32mx5xx/6xx/7xx bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output is disabled 0 = clko output signal is active on the osco pin; the primary oscillator must be disabled or configured for external clock mode (ec) for the clko to be active (poscmod<1:0> = 11 or 00 ) bit 9-8 poscmod<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bit 1 = enable the secondary oscillator 0 = disable the secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdiv) 110 = frcdiv16 fast rc oscillator with fixed divide-by-16 postscaler 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xt+pll, hs+pll, ec+pll) 010 = primary oscillator (xt, hs, ec) (1) 001 = fast rc oscillator with divi de-by-n with pll module (frcdiv+pll) 000 = fast rc oscillator (frc) register 28-2: devcfg1: device configuration word 1 (continued) note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source.
pic32mx5xx/6xx/7xx ds60001156h-page 344 ? 2009-2013 microchip technology inc. register 28-3: devcfg2: d evice configuration word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fpllodiv<2:0> 15:8 r/p r-1 r-1 r-1 r-1 r/p r/p r/p upllen ? ? ? ? upllidiv<2:0> 7:0 r-1 r/p-1 r/p r/p-1 r-1 r/p r/p r/p ? fpllmul<2:0> ? fpllidiv<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-19 reserved: write ? 1 ? bit 18-16 fpllodiv<2:0>: pll output divider bits 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 15 upllen: usb pll enable bit 1 = disable and bypass usb pll 0 = enable usb pll bit 14-11 reserved: write ? 1 ? bit 10-8 upllidiv<2:0>: usb pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 reserved: write ? 1 ? bit 6-4 fpllmul<2:0>: pll multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 reserved: write ? 1 ?
? 2009-2013 microchip technology inc. ds60001156h-page 345 pic32mx5xx/6xx/7xx bit 2-0 fpllidiv<2:0>: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider register 28-3: devcfg2: device configuration word 2 (continued)
pic32mx5xx/6xx/7xx ds60001156h-page 346 ? 2009-2013 microchip technology inc. register 28-4: devcfg3: d evice configuration word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r-1 r-1 r-1 r/p r/p r/p fvbusonio fusbidio ? ? ? fcanio (1) fethio (2) fmiien (2) 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fsrssel<2:0> 15:8 r/p r/p r/p r/p r/p r/p r/p r/p userid<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p userid<7:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 fvbusonio: usb v buson selection bit 1 = vb uson pin is controlled by the usb module 0 = vb uson pin is controlled by the port function bit 30 fusbidio: usb usbid selection bit 1 = usbid pin is controlled by the usb module 0 = usbid pin is controlled by the port function bit 29-27 reserved: write ? 1 ? bit 26 fcanio: can i/o pin selection bit (1) 1 = default can i/o pins 0 = alternate can i/o pins bit 25 fethio: ethernet i/o pin selection bit (2) 1 = default ethernet i/o pins 0 = alternate ethernet i/o pins bit 24 fmiien: ethernet mii enable bit (2) 1 = mii is enabled 0 = rmii is enabled bit 23-19 reserved: write ? 1 ? bit 18-16 fsrssel<2:0>: srs select bits 111 = assign interrupt priority 7 to a shadow register set 110 = assign interrupt priority 6 to a shadow register set ? ? ? 001 = assign interrupt priority 1 to a shadow register set 000 = all interrupt priorities are assigned to a shadow register set bit 15-0 userid<15:0>: user id bits this is a 16-bit value that is user-defined and is readable via icsp? and jtag. note 1: this bit is reserved and reads ? 1 ? on pic32mx664/675/695 devices. 2: this bit is reserved and reads ? 1 ? on pic32mx534/564/575 devices.
? 2009-2013 microchip technology inc. ds60001156h-page 347 pic32mx5xx/6xx/7xx register 28-5: devid: device and revision id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrrrrr ver<3:0> (1) devid<27:24> (1) 23:16 rrrrrrrr devid<23:16> (1) 15:8 rrrrrrrr devid<15:8> (1) 7:0 rrrrrrrr devid<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 ver<3:0>: revision identifier bits (1) bit 27-0 devid<27:0>: device id bits (1) note 1: see the ?pic32 flash programming specification? (ds60001145) for a list of revision and device id values.
pic32mx5xx/6xx/7xx ds60001156h-page 348 ? 2009-2013 microchip technology inc. 28.2 watchdog timer (wdt) this section describes the operation of the wdt and power-up timer of the pic32mx5xx/6xx/7xx. the wdt, when enabled, operates from the internal low-power oscillator (lprc) clock source and can be used to detect system softwa re malfunctions by reset- ting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. key features of the wdt module include: ? configuration or software controlled ? user-configurable time-out period ? can wake the device from sleep or idle figure 28-1: watchdog timer and power-up timer block diagram wake wdtclr = 1 wdt enable lprc power save 25-bit counter pwrt enable wdt enable lprc wdt counter reset control oscillator 25 device reset nmi (wake-up) pwrt pwrt enable fwdtps<4:0> (devcfg1<20:16>) clock decoder 1 1:64 output 0 1 wdt enable reset event
? 2009-2013 microchip technology inc. ds60001156h-page 349 pic32mx5xx/6xx/7xx register 28-6: wdtcon: watc hdog timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1,2) ? ? ? ? ? ? ? 7:0 u-0 r-y r-y r-y r-y r-y r/w-0 r/w-0 ? swdtps<4:0> wd twinen wdtclr legend: y = values set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: watchdog timer enable bit (1,2) 1 = enables the wdt if it is not enabled by the device configuration 0 = disable the wdt if it was enabled in software bit 14-7 unimplemented: read as ? 0 ? bit 6-2 swdtps<4:0>: shadow copy of watchdog timer postscaler value from device configuration bits on reset, these bits are set to the values of the wdtps <4:0> configuration bits. bit 1 wdtwinen: watchdog timer window enable bit 1 = enable windowed watchdog timer 0 = disable windowed watchdog timer bit 0 wdtclr: watchdog timer reset bit 1 = writing a ? 1 ? will clear the wdt 0 = software cannot force this bit to a ? 0 ? note 1: a read of this bit results in a ? 1 ? if the watchdog timer is enabled by the device configuration or software. 2: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit.
pic32mx5xx/6xx/7xx ds60001156h-page 350 ? 2009-2013 microchip technology inc. 28.3 on-chip voltage regulator all pic32mx5xx/6xx/7xx devi ces? core and digital logic are designed to operate at a nominal 1.8v. to simplify system designs, mo st devices in the pic32mx- 5xx/6xx/7xx family incorporate an on-chip regulator providing the required core logic voltage from v dd . a low-esr capacitor (such as tantalum) must be connected to the v cap pin (see figure 28-2 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 31.1 ?dc characteristics? . 28.3.1 on-chip regulator and por it takes a fixed delay for the on-chip regulator to generate an output. during this time, designated as t pu , code execution is disabled. t pu is applied every time the device resumes operation after any power-down, including sleep mode. 28.3.2 on-chip regulator and bor pic32mx5xx/6xx/7xx devi ces also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset (bor). this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specified in section 31.1 ?dc characteristics? . figure 28-2: connections for the on-chip regulator 28.4 programming and diagnostics pic32mx5xx/6xx/7xx devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. these features allow syst em designers to include: ? simplified field programmability using two-wire in-circuit serial pr ogramming? (icsp?) interfaces ? debugging using icsp ? programming and debugging capabilities using the ejtag extension of jtag ? jtag boundary scan testing for device and board diagnostics pic32 devices incorporate two programming and diag- nostic modules, and a trace controller, that provide a range of functions to the application developer. figure 28-3: block diagram of programming, debugging and trace ports note: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. v dd v cap v ss pic32 c efc (2) 3.3v (1) note 1: these are typical operating voltages. refer to section 31.1 ?dc characteristics? for the full operating ranges of v dd . 2: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. (10 ? f typical) tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> instruction trace controller debug<1:0> icesel pgec1 pged1 pgec2 pged2 trclk trd0 trd1 trd2 trd3
? 2009-2013 microchip technology inc. ds60001156h-page 351 pic32mx5xx/6xx/7xx register 28-7: ddpcon: debug data port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 u-0 r/w-0 ? ? ? ?jtagentroen ?tdoen legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 jtagen: jtag port enable bit 1 = enable the jtag port 0 = disable the jtag port bit 2 troen: trace output enable bit 1 = enable the trace port 0 = disable the trace port bit 1 unimplemented: read as ? 0 ? bit 0 tdoen: tdo enable for 2-wire jtag 1 = 2-wire jtag protocol uses tdo 0 = 2-wire jtag protocol does not use tdo
pic32mx5xx/6xx/7xx ds60001156h-page 352 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 353 pic32mx5xx/6xx/7xx 29.0 instruction set the pic32mx5xx/6xx/7xx fa mily instruction set complies with the mips32 release 2 instruction set architecture. the pic32 device family does not support the following features: ? core extend instructions ? coprocessor 1 instructions ? coprocessor 2 instructions note: refer to ?mips32 ? architecture for programmers volume ii: the mips32 ? instruction set? at www.mips.com for more information.
pic32mx5xx/6xx/7xx ds60001156h-page 354 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 355 pic32mx5xx/6xx/7xx 30.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 30.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic32mx5xx/6xx/7xx ds60001156h-page 356 ? 2009-2013 microchip technology inc. 30.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 30.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 30.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 30.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2009-2013 microchip technology inc. ds60001156h-page 357 pic32mx5xx/6xx/7xx 30.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 30.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 30.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 30.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full-speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic32mx5xx/6xx/7xx ds60001156h-page 358 ? 2009-2013 microchip technology inc. 30.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 30.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 30.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demons tration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2009-2013 microchip technology inc. ds60001156h-page 359 pic32mx5xx/6xx/7xx 31.0 electrical characteristics this section provides an overview of the pic32mx5xx/6xx/ 7xx electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic32mx5xx/6xx/7xx devices are listed below. exposure to these maximum rating conditions for extended periods may affect device reliabili ty. functional operation of the device at these or any other conditions, above the parameters indicated in the operat ion listings of this specification, is not implied. absolute maximum ratings (see note 1) ambient temperature under bias................................................................................................. ............-40c to +105c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (note 3) ......................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 2.3v (note 3) ........................................ -0.3v to +5.5v voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v (note 3) ........................................ -0.3v to +3.6v voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v maximum current out of v ss pin(s) .......................................................................................................................3 00 ma maximum current into v dd pin(s) (note 2) ............................................................................................................300 ma maximum output current sunk by any i/o pin............. ........................................................................ .....................25 ma maximum output current sourced by any i/o pin .......... ........................................................................ ..................25 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (note 2) ....................................................................................................200 ma note 1: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional op eration of the device at t hose or any other conditions, above those indicated in the operatio n listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 31-2 ). 3: see the ? pin diagrams ? section for the 5v tolerant pins.
pic32mx5xx/6xx/7xx ds60001156h-page 360 ? 2009-2013 microchip technology inc. 31.1 dc characteristics table 31-1: operating mips vs. voltage characteristic v dd range (in volts) (1) temp. range (in c) max. frequency pic32mx5xx/6xx/7xx dc5 2.3-3.6v -40c to +85c 80 mhz dc5b 2.3-3.6v -40c to +105c 80 mhz note 1: overall functional device operation at v bormin < v dd < v ddmin is tested, but not char acterized. all device analog modules, such as adc, etc., will f unction, but with degraded performance below v ddmin . refer to parameter bo10 in table 31-10 for bor values. table 31-2: thermal operating conditions rating symbol min. typical max. unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c v-temp temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +105 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? s i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = s (({v dd ? v oh } x i oh ) + s (v ol x i ol )) maximum allowed power dissipation p dmax (t j ? t a )/ ? ja w table 31-3: thermal packaging characteristics characteristics symbol typical max. unit see note package thermal resistance, 121-pin tfbga (10x10x1.1 mm) ? ja 40 ? c/w 1 package thermal resistance, 100-pin tqfp (14x14x1 mm) ? ja 43 ? c/w 1 package thermal resistance, 100-pin tqfp (12x12x1 mm) ? ja 43 ? c/w 1 package thermal resistance, 64-pin tqfp (10x10x1 mm) ? ja 47 ? c/w 1 package thermal resistance, 64-pin qfn (9x9x0.9 mm) ? ja 28 ? c/w 1 package thermal resistance, 124-pin vtla (9x9x0.9 mm) ? ja 21 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations.
? 2009-2013 microchip technology inc. ds60001156h-page 361 pic32mx5xx/6xx/7xx table 31-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions operating voltage dc10 v dd supply voltage 2.3 ? 3.6 v ? dc12 v dr ram data retention voltage (1) 1.75 ? ? v ? dc16 v por v dd start voltage to ensure internal power-on reset signal 1.75 ? 2.1 v ? dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.00005 ? 0.115 v/ ? s? note 1: this is the limit to which v dd can be lowered without losing ram data. 2: overall functional device operation at v bormin < v dd < v ddmin is tested, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin . refer to parameter bo10 in table 31-10 for bor values.
pic32mx5xx/6xx/7xx ds60001156h-page 362 ? 2009-2013 microchip technology inc. table 31-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. typical (3) max. units conditions operating current (i dd ) (1,2) for pic32mx575/675/695/775/795 family devices dc20 6 9 ma code executing from flash -40oc, +25oc, +85oc ?4 mhz dc20b 7 10 +105oc dc20a 4 ? code executing from sram ? dc21 37 40 ma code executing from flash ?? 25 mhz (note 4) dc21a 25 ? code executing from sram dc22 64 70 ma code executing from flash ?? 60 mhz (note 4) dc22a 61 ? code executing from sram dc23 85 98 ma code executing from flash -40oc, +25oc, +85oc ? 80 mhz dc23b 90 120 +105oc dc23a 85 ? code executing from sram ? dc25a 125 150 a ? +25c 3.3v lprc (31 khz) (note 4) note 1: a device?s i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, num ber of peripheral modules enabled, internal code execution pattern, execution from program flash me mory vs. sram, i/o pin loading and switching rate, oscillator type, as well as temperature, c an have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu, program flash, and sram data memory are operational, program flash memory wait states = 111 , program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? cpu executing while(1) statement from flash ? rtcc and jtag are disabled 3: data in ?typical? column is at 3.3v, 25c at s pecified operating frequency un less otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 363 pic32mx5xx/6xx/7xx operating current (i dd ) (1,2) for pic32mx534/564/664 /764 family devices dc20c 6 9 ma code executing from flash -40oc, +25oc, +85oc ?4 mhz dc20d 7 10 +105oc dc20e 2 ? code executing from sram ? dc21b 19 32 ma code executing from flash ?? 25 mhz (note 4) dc21c 14 ? code executing from sram dc22b 31 50 ma code executing from flash ?? 60 mhz (note 4) dc22c 29 ? code executing from sram dc23c 39 65 ma code executing from flash -40oc, +25oc, +85oc ? 80 mhz dc23d 49 70 +105oc dc23e 39 ? code executing from sram ? dc25b 100 150 a ? +25c 3.3v lprc (31 khz) (note 4) table 31-5: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. typical (3) max. units conditions note 1: a device?s i dd supply current is mainly a function of t he operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, num ber of peripheral modules enabled, internal code execution pattern, execution from program flash me mory vs. sram, i/o pin l oading and switching rate, oscillator type, as well as temperature, c an have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu, program flash, and sram data memory are operational, program flash memory wait states = 111 , program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? cpu executing while(1) statement from flash ? rtcc and jtag are disabled 3: data in ?typical? column is at 3.3v, 25c at s pecified operating frequency un less otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 364 ? 2009-2013 microchip technology inc. table 31-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp parameter no. typical (2) max. units conditions idle current (i idle ) (1) for pic32mx575/675/695/775/795 family devices dc30 4.5 6.5 ma -40oc, +25oc, +85oc ?4 mhz dc30b 5 7 +105c dc31 13 15 ma -40oc, +25oc, +85oc ? 25 mhz (note 3) dc32 28 30 ma -40oc, +25oc, +85oc ? 60 mhz (note 3) dc33 36 42 ma -40oc, +25oc, +85oc ?80 mhz dc33b 39 45 ma +105c dc34 ? 40 a -40c 2.3v lprc (31 khz) (note 3) dc34a 75 +25c dc34b 800 +85c dc34c 1000 +105c dc35 35 ?a -40c 3.3v dc35a 65 +25c dc35b 600 +85c dc35c 800 +105c dc36 ? 43 a -40c 3.6v dc36a 106 +25c dc36b 800 +85c dc36c 1000 +105c note 1: the test conditions for i idle current measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in idle mode, progra m flash memory wait states = 111 , program cache and prefetch are dis- abled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 365 pic32mx5xx/6xx/7xx idle current (i idle ) (1) for pic32mx534/564/664/764 family devices dc30a 1.5 5 ma -40oc, +25oc, +85oc ?4 mhz dc30c 3.5 6 +105oc dc31a 7 11 -40oc, +25oc, +85oc ? 25 mhz (note 3) dc32a 13 20 ma -40oc, +25oc, +85oc ? 60 mhz (note 3) dc33a 17 25 ma -40oc, +25oc, +85oc ?80 mhz dc33c 20 27 +105oc dc34c ? 40 a -40c 2.3v lprc (31 khz) (note 3) dc34d 75 +25c dc34e 800 +85c dc34f 1000 +105oc dc35c 30 ?a -40c 3.3v dc35d 55 +25c dc35e 230 +85c dc35f 800 +105oc dc36c ? 43 a -40c 3.6v dc36d 106 +25c dc36e 800 +85c dc36f 1000 +105oc table 31-6: dc characteristics: idle current (i idle ) (continued) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp parameter no. typical (2) max. units conditions note 1: the test conditions for i idle current measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in idle mode, program flash memory wait states = 111 , program cache and prefetch are dis- abled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 366 ? 2009-2013 microchip technology inc. table 31-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. typical (2) max. units conditions power-down current (i pd ) (1) for pic32mx575/675/695/775/795 family devices dc40 10 40 ? a -40c 2.3v base power-down current (note 6) dc40a 36 100 +25c dc40b 400 720 +85c dc40h 900 1800 +105c dc40c 41 120 +25c 3.3v base power-down current dc40d 22 80 -40c 3.6v base power-down current dc40e 42 120 +25c dc40g 315 400 (5) +70c dc40f 410 800 +85c dc40i 1000 2000 +105c module differential current for pi c32mx575/675/695/775/ 795 family devices dc41 ? 10 ? a? 2.3v watchdog timer current: ? i wdt (notes 3,6) dc41a 5 ? 3.3v watchdog timer current: ? i wdt (note 3) dc41b ? 20 3.6v watchdog timer current: ? i wdt (note 3) dc42 ? 40 ? a? 2.3v rtcc + timer1 w/32 khz crystal: ? i rtcc (notes 3,6) dc42a 23 ? 3.3v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc42b ? 50 3.6v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc43 ? 1300 ? a? 2.5v adc: ? i adc (notes 3,4,6) dc43a 1100 ? 3.3v adc: ? i adc (notes 3,4) dc43b ? 1300 3.6v adc: ? i adc (notes 3,4) note 1: the test conditions for i pd current measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in sleep mode, program flash memory wait states = 111 , program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled 2: data in the ?typical? column is at 3.3v, 25c unle ss otherwise stated. parameters are for design guidance only and are not tested. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current ar e as follows: internal adc rc oscillator enabled. 5: data is characterized at +70c and not tested. parameter is for design guidance only. 6: this parameter is characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 367 pic32mx5xx/6xx/7xx power-down current (i pd ) (1) for pic32mx534/564/6 64/764 family devices dc40g 12 40 ? a -40c 2.3v base power-down current (note 6) dc40h 20 120 +25c dc40i 210 600 +85c dc40o 400 1000 +105c dc40j 20 120 +25c 3.3v base power-down current dc40k 15 80 -40c 3.6v base power-down current dc40l 20 120 +25c dc40m 113 350 (5) +70c dc40n 220 650 +85c dc40p 500 1000 +105c module differential current for pi c32mx534/564/664/764 family devices dc41c ? 10 ? a? 2.5v watchdog timer current: ? i wdt (notes 3,6) dc41d 5 ? 3.3v watchdog timer current: ? i wdt (note 3) dc41e ? 20 3.6v watchdog timer current: ? i wdt (note 3) dc42c ? 40 ? a? 2.5v rtcc + timer1 w/32 khz crystal: ? i rtcc (notes 3,6) dc42d 23 ? 3.3v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc42e ? 50 3.6v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc43c ? 1300 ? a? 2.5v adc: ? i adc (notes 3,4,6) dc43d 1100 ? 3.3v adc: ? i adc (notes 3,4) dc43e ? 1300 3.6v adc: ? i adc (notes 3,4) table 31-7: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. typical (2) max. units conditions note 1: the test conditions for i pd current measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in sleep mode, program flash memory wait states = 111 , program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ) ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled 2: data in the ?typical? column is at 3.3v, 25c unle ss otherwise stated. parameters are for design guidance only and are not tested. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current are as follows: internal adc rc oscillator enabled. 5: data is characterized at +70c and not tested. parameter is for design guidance only. 6: this parameter is characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 368 ? 2009-2013 microchip technology inc. table 31-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions v il input low voltage di10 i/o pins: with ttl buffer v ss ?0.15v dd v with schmitt trigger buffer v ss ?0.2v dd v di15 mclr (2) v ss ?0.2v dd v di16 osc1 (xt mode) v ss ?0.2v dd v (note 4) di17 osc1 (hs mode) v ss ?0.2v dd v (note 4) di18 sdax, sclx v ss ?0.3v dd v smbus disabled (note 4) di19 sdax, sclx v ss ? 0.8 v smbus enabled (note 4) v ih input high voltage di20 i/o pins not 5v-tolerant (5) 0.65 v dd ?v dd v (note 4,6) i/o pins 5v-tolerant with pmp (5) 0.25 v dd + 0.8v ? 5.5 v (note 4,6) i/o pins 5v-tolerant (5) 0.65 v dd ?5.5v di28 sdax, sclx 0.65 v dd ? 5.5 v smbus disabled (note 4,6) di29 sdax, sclx 2.1 ? 5.5 v smbus enabled, 2.3v ? v pin ? 5.5 (note 4,6) di30 i cnpu change notification pull-up current ??-50 ? av dd = 3.3v, v pin = v ss (note 3,6) di31 i cnpd change notification pull-down current (4) ?50?av dd = 3.3v, v pin = v dd note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v-tolerant pins. 6: the v ih specification is only in relation to externally applied inputs and not with re spect to the user-select- able pull-ups. externally applied high impedance or open drain input signals utilizing the pic32 internal pull- ups are guaranteed to be recognized as a logic ?high? internally to the pic32 device, provided that the external load does not exceed the maximum value of i cnpu . 7: v il source < (v ss - 0.3). characterized but not tested. 8: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 9: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any ?positive? input injection current. 10: injection currents > | 0 | can affect the adc re sults by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 11: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the ?absolute instantaneous? sum of the input inje ction currents from all pins do not exceed the speci- fied limit. if note 7 , i icl = (((vss - 0.3) - v il source) / rs). if note 8 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injec- tion current = 0 .
? 2009-2013 microchip technology inc. ds60001156h-page 369 pic32mx5xx/6xx/7xx i il input leakage current (3) di50 i/o ports ? ? + 1 ? av ss ? v pin ? v dd , pin at high-impedance di51 analog input pins ? ? + 1 ? av ss ? v pin ? v dd , pin at high-impedance di55 mclr (2) ??+ 1 ? av ss ?? v pin ?? v dd di56 osc1 ? ? + 1 ? av ss ?? v pin ?? v dd , xt and hs modes di60a i icl input low injection current 0?-5 (7,10) ma this parameter applies to all pins, with the exception of rb10. maximum i ich current for this exception is 0ma. di60b i ich input high injection current 0?+5 (8,9,10) ma this parameter applies to all pins, with the exception of all 5v toler- ant pins, sosci, and rb10. maximum i ich current for these exceptions is 0 ma. di60c ? i ict total input injection current (sum of all i/o and control pins) -20 (11) ?+20 (11) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) ? ? i ict table 31-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating co nditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v-tolerant pins. 6: the v ih specification is only in relation to externally applied inputs and not with re spect to the user-select- able pull-ups. externally applied high impedance or open drain input signals utilizing the pic32 internal pull- ups are guaranteed to be recognized as a logic ?high? internally to the pic32 device, provided that the external load does not exceed the maximum value of i cnpu . 7: v il source < (v ss - 0.3). characterized but not tested. 8: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 9: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any ?positive? input injection current. 10: injection currents > | 0 | can affect the adc re sults by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 11: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the ?absolute instantaneous? sum of the input inje ction currents from all pins do not exceed the speci- fied limit. if note 7 , i icl = (((vss - 0.3) - v il source) / rs). if note 8 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injec- tion current = 0 .
pic32mx5xx/6xx/7xx ds60001156h-page 370 ? 2009-2013 microchip technology inc. table 31-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins - all i/o output pins not defined as 8x sink driver pins ??0.4v i ol ? 10 ma, v dd = 3.3v output low voltage i/o pins: 8x sink driver pins - rc15 ??0.4vi ol ? 15 ma, v dd = 3.3v do20 v oh output high voltage i/o pins: 4x source driver pins - all i/o output pins not defined as 8x source driver pins 2.4 ? ? v i oh ? -10 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - rc15 2.4 ? ? v i oh ? -15 ma, v dd = 3.3v do20a v oh 1 output high voltage i/o pins: 4x source driver pins - all i/o output pins not defined as 8x sink driver pins 1.5 (1) ?? v i oh ? -14 ma, v dd = 3.3v 2.0 (1) ?? i oh ? -12 ma, v dd = 3.3v 3.0 (1) ?? i oh ? -7 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - rc15 1.5 (1) ?? v i oh ? -22 ma, v dd = 3.3v 2.0 (1) ?? i oh ? -18 ma, v dd = 3.3v 3.0 (1) ?? i oh ? -10 ma, v dd = 3.3v note 1: parameters are characterized, but not tested. 2: this driver pin only applies to devices with less than 64 pins. 3: this driver pin only applies to devices with 64 pins. table 31-10: electrical characteristics: bor dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. (1) typical max. units conditions bo10 v bor bor event on v dd transition high-to-low ( note 2 ) 2.0 ? 2.3 v ? note 1: parameters are for design guidance only and are not tested in manufacturing. 2: overall functional device operation at v bormin < v dd < v ddmin is tested, but not characterized. all device analog modules, such as adc, etc., will f unction, but with degraded performance below v ddmin .
? 2009-2013 microchip technology inc. ds60001156h-page 371 pic32mx5xx/6xx/7xx table 31-12: program flash memory wait state characteristics table 31-11: dc characteristics: program memory dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions program flash memory (3) d130 e p cell endurance 1000 ? ? e/w ? d130a e p cell endurance 20,000 ? ? e/w see note 4 d131 v pr v dd for read 2.3 ? 3.6 v ? d132 v pew v dd for erase or write 3.0 ? 3.6 v ? d132a v pew v dd for erase or write 2.3 ? 3.6 v see note 4 d134 t retd characteristic retention 20 ? ? year p rovided no other specifications are violated d135 i ddp supply current during programming ?10 ?ma ? t ww word write cycle time 20 ? 40 ? s? d136 t rw row write cycle time (2) 34.5?ms ? d137 t pe page erase cycle time 20 ? ? ms ? t ce chip erase cycle time 80 ? ? ms ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the minimum sysclk for row programming is 4 mhz. care should be taken to minimize bus activities during row programming, such as suspending any me mory-to-memory dma operations. if heavy bus loads are expected, selecting bus matrix arbitration mode 2 (rotating priority) may be necessary. the default arbitration mode is mode 1 (cpu has lowest priority). 3: refer to ?pic32 flash programming specification? (ds60001145) for operating conditions during programming and erase cycles. 4: this parameter only applies to pic32mx534/564/664/764 devices. dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp required flash wait states sysclk units comments 0 wait state 0 to 30 mhz ? 1 wait state 31 to 60 2 wait states 61 to 80
pic32mx5xx/6xx/7xx ds60001156h-page 372 ? 2009-2013 microchip technology inc. table 31-13: comparator specifications dc characteristics standard operating conditions (see note 3): 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage ? 7.5 25 mv a vdd = v dd , a vss = v ss d301 v icm input common mode voltage 0 ? v dd va vdd = v dd , a vss = v ss (note 2) d302 cmrr common mode rejection ratio 55 ? ? db max v icm = (v dd - 1)v (note 2) d303 t resp response time ? 150 400 ns av dd = v dd , av ss = v ss (notes 1, 2) d304 on2 ov comparator enabled to output valid ??10 ? s comparator module is configured before setting the comparator on bit (note 2) d305 iv ref internal voltage reference 0.57 0.6 0.63 v for devices without bgsel<1:0> 1.14 1.2 1.26 v bgsel<1:0> = 00 0.57 0.6 0.63 v bgsel<1:0> = 01 note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . 2: these parameters are characterized but not tested. 3: the comparator module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionalit y is tested, but not characterized.
? 2009-2013 microchip technology inc. ds60001156h-page 373 pic32mx5xx/6xx/7xx table 31-14: voltage reference specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units comments d310 v res resolution v dd /24 ? v dd /32 lsb ? d311 vr aa absolute accuracy ? ? 1/2 lsb ? d312 t set settling time (1) ? ? 10 ? s? d313 v iref internal voltage reference ? 0.6 ? v ? note 1: settling time measured while cvrr = 1 and cvr<3:0> transitions from ? 0000 ? to ? 1111 ?. this parameter is characterized, but not tested in manufacturing. table 31-15: internal voltage regulator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units comments d321 c efc external filter capacitor value 8 10 ? ? f capacitor must be low series resistance (1 ohm) d322 t pwrt power-up timer period ? 64 ? ms ?
pic32mx5xx/6xx/7xx ds60001156h-page 374 ? 2009-2013 microchip technology inc. 31.2 ac characteristics and timing parameters the information contained in this section defines pic32mx5xx/6xx/7xx ac characteristics and timing parameters. figure 31-1: load conditions for device timing specifications figure 31-2: external clock timing v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins 50 pf for osc2 pin (ec mode) load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 table 31-16: capacitive loading requirements on output pins ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. osc1 os20 os30 os30 os31 os31
? 2009-2013 microchip technology inc. ds60001156h-page 375 pic32mx5xx/6xx/7xx table 31-17: external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions os10 f osc external clki frequency (external clocks only allowed in ec and ecpll modes) dc 4 ? ? 50 50 mhz mhz ec (note 4) ecpll (note 3) os11 oscillator crystal frequency 3 ? 10 mhz xt (note 4) os12 4 ? 10 mhz xtpll (notes 3,4) os13 10 ? 25 mhz hs (note 5) os14 10 ? 25 mhz hspll (notes 3,4) os15 32 32.768 100 khz s osc (note 4) os20 t osc t osc = 1/f osc = t cy (2) ? ? ? ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) high or low time 0.45 x t osc ??nsec (note 4) os31 t os r, t os f external clock in (osc1) rise or fall time ? ? 0.05 x t osc ns ec (note 4) os40 t ost oscillator start-up timer period (only applies to hs, hspll, xt, xtpll and s osc clock oscillator modes) ?1024?t osc (note 4) os41 t fscm primary clock fail safe time-out period ?2?ms (note 4) os42 g m external oscillator transconductance ?12?ma/vv dd = 3.3v, t a = +25c (note 4) note 1: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are characterized but are not tested. 2: instruction cycle period (t cy ) equals the input oscillator time base period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. 3: pll input requirements: 4 mh z ? f pllin ? 5 mh z (use pll prescaler to reduce f osc ). this parameter is characterized, but is only test ed at 10 mhz at manufacturing. 4: this parameter is characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 376 ? 2009-2013 microchip technology inc. table 31-18: pll clock timing specifications (v dd = 2.3v to 3.6v) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 3.92 ? 5 mhz ecpll, hspll, xtpll, frcpll modes os51 f sys on-chip vco system frequency 60 ? 120 mhz ? os52 t lock pll start-up time (lock time) ? ? 2 ms ? os53 d clk clko stability (2) (period jitter or cumulative) -0.25 ? +0.25 % measured over 100 ms period note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by cl ock-cycle measurements. to get the effective jitter for individual time-bases on communicat ion clocks, use t he following formula: for example, if sysclk = 80 mhz and spi bit rate = 20 mhz, the effective jitter is as follows: effectivejitter d clk sysclk communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 80 20 ----- - ------------- - d clk 2 ------------- - == table 31-19: internal frc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. characteristics min. typical max. units conditions internal frc accuracy @ 8.00 mhz (1) for pic32mx575/675/695/775/795 family devices f20a frc -2 ? +2 % ? internal frc accuracy @ 8.00 mhz (1) for pic32mx534/564/664/764 family devices f20b frc -0.9 ? +0.9 % ? note 1: frequency calibrated at 25c and 3.3v. the tun bits can be used to compensate for temperature drift.
? 2009-2013 microchip technology inc. ds60001156h-page 377 pic32mx5xx/6xx/7xx figure 31-3: i/o timing characteristics table 31-20: internal rc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. characteristics min. typical max. units conditions lprc @ 31.25 khz (1) f21 lprc -15 ? +15 % ? note 1: change of lprc frequency as v dd changes. note: refer to figure 31-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31 do32 table 31-21: i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (2) min. typical (1) max. units conditions do31 t io r port output rise time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v do32 t io f port output fall time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v di35 t inp intx pin high or low time 10 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t sysclk ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 378 ? 2009-2013 microchip technology inc. figure 31-4: power-on reset timing characteristics v dd v por note 1: the power-up period will be extended if the power-up sequence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) sy10 cpu starts fetching code clock sources = (hs, h spll, xt, xtpll and s osc ) v dd v por sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (note 1) (note 1) clock sources = (frc, frcdiv, frcdi v16, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02
? 2009-2013 microchip technology inc. ds60001156h-page 379 pic32mx5xx/6xx/7xx figure 31-5: external reset timing characteristics table 31-22: resets timing ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled ?400600 ? s -40c to +85c sy02 t sysdly system delay period: time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. ?1 s + 8 sysclk cycles ? ? -40c to +85c sy20 t mclr mclr pulse width (low) ? 2 ? ? s -40c to +85c sy30 t bor bor pulse width (low) ? 1 ? ? s -40c to +85c note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. characterized by design but not tested. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, f rcdiv, frcdiv16, frcpll , ec, ecpll and lprc) clock sources = (hs, h spll, xt, xtpll and s osc ) (t sysdly ) sy02 (t sysdly ) sy02
pic32mx5xx/6xx/7xx ds60001156h-page 380 ? 2009-2013 microchip technology inc. figure 31-6: timer1, 2, 3, 4, 5 externa l clock timing characteristics note: refer to figure 31-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 31-23: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (2) min. typical max. units conditions ta10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta15 t tx ptxck input period synchronous, with prescaler [(greater of 25 ns or 2 t pb )/n] + 30 ns ??nsv dd > 2.7v [(greater of 25 ns or 2 t pb )/n] + 50 ns ??nsv dd < 2.7v asynchronous, with prescaler 20 ? ? ns v dd > 2.7v (note 3) 50 ? ? ns v dd < 2.7v (note 3) os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 ? 100 khz ? ta20 t ckextmrl delay from external txck clock edge to timer increment ??1t pb ? note 1: timer1 is a type a. 2: this parameter is characterized, but not tested in manufacturing. 3: n = prescale value (1, 8, 64, 256).
? 2009-2013 microchip technology inc. ds60001156h-page 381 pic32mx5xx/6xx/7xx table 31-24: timer2, 3, 4, 5 external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions tb10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 n = prescale value (1, 2, 4, 8, 16, 32, 64, 256) tb11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 tb15 t tx ptxck input period synchronous, with prescaler [(greater of [(25 ns or 2 t pb )/n] + 30 ns ?nsv dd > 2.7v [(greater of [(25 ns or 2 t pb )/n] + 50 ns ?nsv dd < 2.7v tb20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 382 ? 2009-2013 microchip technology inc. figure 31-7: input capture (capx) timing characteristics figure 31-8: output compare module (ocx) timing characteristics table 31-26: output compare module timing requirements icx ic10 ic11 ic15 note: refer to figure 31-1 for load conditions. table 31-25: input capture module timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. ic15 t cc p icx input period [(25 ns or 2 t pb )/n] + 50 ns ?ns ? note 1: these parameters are characterized, but not tested in manufacturing. ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ? ? ? ns see parameter do32 oc11 t cc r ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters ar e for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 31-1 for load conditions. or pwm mode)
? 2009-2013 microchip technology inc. ds60001156h-page 383 pic32mx5xx/6xx/7xx figure 31-9: ocx/pwm module timing characteristics ocfa/ocfb ocx oc20 oc15 note: refer to figure 31-1 for load conditions. ocx is tri-stated table 31-27: simple ocx/pwm mode timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 50 ns ? oc20 t flt fault input pulse width 50 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless other wise stated. parameters are for design guidance only and are not tested.
pic32mx5xx/6xx/7xx ds60001156h-page 384 ? 2009-2013 microchip technology inc. figure 31-10: spix module master mode (cke = 0 ) timing characteristics table 31-28: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (3) t sck /2 ??ns ? sp20 t sc f sckx output fall time (4) ???ns see parameter do32 sp21 t sc r sckx output rise time (4) ? ?? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ?? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ?? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 ns v dd > 2.7v ?? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ??ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 31-1 for load conditions.
? 2009-2013 microchip technology inc. ds60001156h-page 385 pic32mx5xx/6xx/7xx figure 31-11: spix module master mode (cke = 1 ) timing characteristics table 31-29: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (3) t sck /2 ? ? ns ? sp20 t sc f sckx output fall time (4) ? ? ? ns see parameter do32 sp21 t sc r sckx output rise time (4) ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ??15nsv dd > 2.7v ??20nsv dd < 2.7v sp36 t do v2 sc , t do v2 sc l sdox data output setup to first sckx edge 15 ? ? ns ? sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 31-1 for load conditions. sp11 sp10 sp21 sp20 sp40 sp41 sp20 sp21 msb in
pic32mx5xx/6xx/7xx ds60001156h-page 386 ? 2009-2013 microchip technology inc. figure 31-12: spix module slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 31-1 for load conditions. sdi x msb in table 31-30: spix module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? ? ? ns see parameter do32 sp73 t sc r sckx input rise time ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? ? 15 ns v dd > 2.7v ? ? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx input 175 ? ? ns ? sp51 t ss h2 do z ssx ? to sdox output high-impedance (3) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
? 2009-2013 microchip technology inc. ds60001156h-page 387 pic32mx5xx/6xx/7xx figure 31-13: spix module slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp40 sp41 note: refer to figure 31-1 for load conditions. sp50 sp70 sp35 table 31-31: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? 5 10 ns ? sp73 t sc r sckx input rise time ? 5 10 ns ? sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? ? 20 ns v dd > 2.7v ? ? 30 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx ? input 175 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
pic32mx5xx/6xx/7xx ds60001156h-page 388 ? 2009-2013 microchip technology inc. sp51 t ss h2 do z ssx ? to sdo x output high-impedance (4) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx ? after sckx edge t sck + 20 ??ns ? sp60 t ss l2 do v sdox data output valid after ssx edge ? ? 25 ns ? table 31-31: spix module slave mode (cke = 1 ) timing requirements (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
? 2009-2013 microchip technology inc. ds60001156h-page 389 pic32mx5xx/6xx/7xx figure 31-14: i2cx bus start/stop bits timing characteristics (master mode) figure 31-15: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 31-1 for load conditions. im30 im31 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 31-1 for load conditions.
pic32mx5xx/6xx/7xx ds60001156h-page 390 ? 2009-2013 microchip technology inc. table 31-32: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pb * (brg + 2) ? ? s? 400 khz mode t pb * (brg + 2) ? ? s? 1 mhz mode (2) t pb * (brg + 2) ? ? s? im11 t hi : scl clock high time 100 khz mode t pb * (brg + 2) ? ? s? 400 khz mode t pb * (brg + 2) ? ? s? 1 mhz mode (2) t pb * (brg + 2) ? ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) 100 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? ? s? 400 khz mode 0 0.9 ? s 1 mhz mode (2) 0 0.3 ? s im30 t su : sta start condition setup time 100 khz mode t pb * (brg + 2) ? ns only relevant for repeated start condition 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im31 t hd : sta start condition hold time 100 khz mode t pb * (brg + 2) ? ns after this period, the first clock pulse is generated 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im33 t su : sto stop condition setup time 100 khz mode t pb * (brg + 2) ? ns ? 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im34 t hd : sto stop condition 100 khz mode t pb * (brg + 2) ? ns ? hold time 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ? 350 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode (2) 0.5 ? ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay (3) 52 312 ns ? note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (only for 1 mhz mode).
? 2009-2013 microchip technology inc. ds60001156h-page 391 pic32mx5xx/6xx/7xx figure 31-16: i2cx bus start/stop bits timing characteristics (slave mode) figure 31-17: i2cx bus data timing characteristics (slave mode) is34 sclx sdax start condition stop condition is33 note: refer to figure 31-1 for load conditions. is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 31-1 for load conditions.
pic32mx5xx/6xx/7xx ds60001156h-page 392 ? 2009-2013 microchip technology inc. table 31-33: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? ? s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 ? ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? ? s pbclk must operate at a minimum of 800 khz 400 khz mode 0.6 ? ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?100ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?300ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 ? s 1 mhz mode (1) 00.3 ? s is30 t su : sta start condition setup time 100 khz mode 4700 ? ns only relevant for repeated start condition 400 khz mode 600 ? ns 1 mhz mode (1) 250 ? ns is31 t hd : sta start condition hold time 100 khz mode 4000 ? ns after this period, the first clock pulse is generated 400 khz mode 600 ? ns 1 mhz mode (1) 250 ? ns is33 t su : sto stop condition setup time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 600 ? ns is34 t hd : sto stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode (1) 0.5 ? ? s is50 c b bus capacitive loading ? 400 pf ? note 1: maximum pin capacitance = 10 pf for all i2cx pins (only for 1 mhz mode).
? 2009-2013 microchip technology inc. ds60001156h-page 393 pic32mx5xx/6xx/7xx figure 31-18: can module i/o timing characteristics table 31-34: can module i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ? ? ? ns see parameter do32 ca11 tior port output rise time ? ? ? ns see parameter do31 ca20 tcwf pulse width to trigger can wake-up filter 700 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. citx pin (output) ca10 ca11 old value new value ca20 cirx pin (input)
pic32mx5xx/6xx/7xx ds60001156h-page 394 ? 2009-2013 microchip technology inc. table 31-35: ethernet module specifications figure 31-19: mdio sourced by the pic32 device figure 31-20: mdio sourced by the phy ac characteristics standard operating conditions (see note 1): 2.9v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. characteristic min. typical max. units conditions miim timing requirements et1 mdc duty cycle 40 ? 60 % ? et2 mdc period 400 ? ? ns ? et3 mdio output setup and hold 10 ? 10 ns see figure 31-19 et4 mdio input setup and hold 0 ? 300 ns see figure 31-20 mii timing requirements et5 tx clock frequency ? 25 ? mhz ? et6 tx clock duty cycle 35 ? 65 % ? et7 etxdx, eten, etxerr output delay 0 ? 25 ns see figure 31-21 et8 rx clock frequency ? 25 ? mhz ? et9 rx clock duty cycle 35 ? 65 % ? et10 erxdx, erxdv, erxerr setup and hold 10 ? 30 ns see figure 31-22 rmii timing requirements et11 reference clock frequency ? 50 ? mhz ? et12 reference clock duty cycle 35 ? 65 % ? et13 etxdx, eten, setup and hold 2 ? 16 ns ? et14 erxdx, erxdv, erxerr setup and hold 2 ? 16 ns ? note 1: the ethernet module is functional at v bormin < v dd < 2.9v, but with degraded performance. unless other- wise stated, module functionality is tested, but not characterized. et3 (hold) (setup) et3 mdc mdio v ihmin v ilmax v ihmin v ilmax v ihmin v ilmax v ihmin v ilmax et4 mdc mdio
? 2009-2013 microchip technology inc. ds60001156h-page 395 pic32mx5xx/6xx/7xx figure 31-21: transmit signal ti ming relationships at the mii figure 31-22: receive signal timi ng relationships at the mii et7 tx clock etxd<3:0>, v ihmin v ilmax v ihmin v ilmax eten, etxerr et10 (hold) rx clock erxd<3:0>, v ihmin v ilmax v ihmin v ilmax (setup) et10 erxdv, erxerr
pic32mx5xx/6xx/7xx ds60001156h-page 396 ? 2009-2013 microchip technology inc. table 31-36: adc module specifications ac characteristics standard operating conditions (see note 5): 2.5v to 3.6v (unless otherwise stated) operating te mperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.5 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ?v ss + 0.3 v ? reference inputs ad05 ad05a v refh reference voltage high av ss + 2.0 2.5 ? ? av dd 3.6 v v (note 1) v refh = av dd (note 3) ad06 v refl reference voltage low av ss ?v refh ? 2.0 v (note 1) ad07 v ref absolute reference voltage (v refh ? v refl ) 2.0 ? av dd v (note 3) ad08 ad08a i ref current drain ? ? 250 ? 400 3 ? a ? a adc operating adc off analog input ad12 v inh -v inl full-scale input span v refl ?v refh v? ad13 v inl absolute v inl input voltage av ss ? 0.3 ? av dd /2 v ? ad14 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ? ad15 leakage current ? 0.001 0.610 ? av inl = av ss = v refl = 0v, av dd = v refh = 3.3v source impedance = 10 k ? ad17 r in recommended impedance of analog voltage source ??5k ? (note 1) adc accuracy ? measurements with external v ref +/v ref - ad20c nr resolution 10 data bits bits ? ad21c inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v (note 2) ad23c g err gain error > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24c e off offset error > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 3.3v ad25c ? monotonicity ? ? ? ? guaranteed note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: the adc module is functional at v bormin < v dd < 2.5v, but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized.
? 2009-2013 microchip technology inc. ds60001156h-page 397 pic32mx5xx/6xx/7xx adc accuracy ? measurements with internal v ref +/v ref - ad20d nr resolution 10 data bits bits (note 3) ad21d inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad22d dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (notes 2,3) ad23d g err gain error > -4 ? < 4 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad24d e off offset error > -2 ? < 2 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad25d ? monotonicity ? ? ? ? guaranteed dynamic performance ad31b sinad signal to noise and distortion 55 58.5 ? db (notes 3,4) ad34b enob effective number of bits 9.0 9.5 ? bits (notes 3,4) table 31-36: adc module specifications (continued) ac characteristics standard operating conditions (see note 5): 2.5v to 3.6v (unless otherwise stated) operating te mperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: the adc module is functional at v bormin < v dd < 2.5v, but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized.
pic32mx5xx/6xx/7xx ds60001156h-page 398 ? 2009-2013 microchip technology inc. table 31-37: 10-bit adc conversion rate parameters standard operating conditions (see note 3): 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ?? t a ? +105c for v-temp adc speed (2) t ad minimum sampling time minimum r s maximum v dd adc channels configuration 1 msps to 400 ksps (1) 65 ns 132 ns 500 ? 3.0v to 3.6v up to 400 ksps 200 ns 200 ns 5.0 k ? 2.5v to 3.6v note 1: external v ref - and v ref + pins must be used for correct operation. 2: these parameters are characterized, but not tested in manufacturing. 3: the adc module is functional at v bormin < v dd < 2.5v, but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. v ref -v ref + adc an x s&h ch x v ref -v ref + adc an x s&h ch x an x or v ref - or av ss or av dd
? 2009-2013 microchip technology inc. ds60001156h-page 399 pic32mx5xx/6xx/7xx table 31-38: analog-to-digital co nversion timing requirements ac characteristics standard operating conditions (see note 4): 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions clock parameters ad50 t ad analog-to-digital clock period (2) 65 ? ? ns see table 31-37 conversion rate ad55 tconv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate (sampling speed) ? ? 1000 ksps av dd = 3.0v to 3.6v ? ? 400 ksps av dd = 2.5v to 3.6v ad57 t samp sample time 1 t ad ???t samp must be ? 132 ns timing parameters ad60 tpcs conversion start from sample trigger (3) ?1.0 t ad ? ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 tpss sample start from setting sample (samp) bit 0.5 t ad ? 1.5 t ad ?? ad62 tcss conversion completion to sample start (asam = 1 ) (3) ?0.5 t ad ?? ? ad63 tdpu time to stabilize analog stage from analog-to-digital off to analog-to-digital on (3) ?? 2 ? s? note 1: these parameters are characterized, but not tested in manufacturing. 2: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 3: characterized by design but not tested. 4: the adc module is functional at v bormin < v dd < 2.5v, but with degraded per formance. unless otherwise stated, module functionality is tested, but not characterized.
pic32mx5xx/6xx/7xx ds60001156h-page 400 ? 2009-2013 microchip technology inc. figure 31-23: analog-to-digital co nversion (10-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ad60 conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in section 17. ?10-bi t a/d converter? (ds60001104) of the 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 ch0_samp eoc 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution ?pic32 family reference manual? .
? 2009-2013 microchip technology inc. ds60001156h-page 401 pic32mx5xx/6xx/7xx figure 31-24: analog-to-digital conversion (10-bit mode) timing characteristics (asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp set adon adclk instruction samp ch0_dischrg conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. ad50 ch0_samp eoc 7 3 ad55 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. t samp t conv 3 4 execution t samp is described in section 17. ?10-bit a/d converter? (ds60001104) of the ?pic32 family reference manual .
pic32mx5xx/6xx/7xx ds60001156h-page 402 ? 2009-2013 microchip technology inc. figure 31-25: parallel slave port timing cs rd wr pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 31-39: parallel slave port requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions ps1 tdtv2wrh data in valid before wr or cs inactive (setup time) 20 ? ? ns ? ps2 twrh2dti wr or cs inactive to data-in invalid (hold time) 40 ? ? ns ? ps3 trdl2dtv rd and cs active to data-out valid ? ? 60 ns ? ps4 trdh2dti rd active ? or cs inactive to data-out invalid 0 ? 10 ns ? ps5 tcs cs active time t pb + 40 ? ? ns ? ps6 t wr wr active time t pb + 25 ? ? ns ? ps7 t rd rd active time t pb + 25 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 403 pic32mx5xx/6xx/7xx figure 31-26: parallel master port read timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmrd pmcs<2:1> pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 table 31-40: parallel master port read timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions pm1 t lat pmall/pmalh pulse width ? 1 t pb ?? ? pm2 t adsu address out valid to pmall/ pmalh invalid (address setup time) ?2 t pb ?? ? pm3 t adhold pmall/pmalh invalid to address out invalid (add ress hold time) ?1 t pb ?? ? pm4 t ahold pmrd inactive to address out invalid (address hold time) 5??ns ? pm5 t rd pmrd pulse width ? 1 t pb ?? ? pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 15 ? ? ns ? pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) ?80?ns ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 404 ? 2009-2013 microchip technology inc. figure 31-27: parallel master port write timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmwr pmcs<2:1> pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 table 31-41: parallel master po rt write timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions pm11 t wr pmwr pulse width ? 1 t pb ?? ? pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) ?2 t pb ?? ? pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) ?1 t pb ?? ? note 1: these parameters are characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 405 pic32mx5xx/6xx/7xx table 31-42: usb otg electrical specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions usb313 v usb 3 v 3 usb voltage 3.0 ? 3.6 v voltage on v usb 3 v 3 must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ? ? 0.8 v ? usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v ? usb318 v difs differential input sensitivity ? ? 0.2 v the difference between d+ and d- must exceed this value while vcm is met usb319 vcm differential common mode range 0.8 ? 2.5 v ? usb320 z out driver output impedance 28.0 ? 44.0 ? ? usb321 v ol voltage output low 0.0 ? 0.3 v 14.25 k ? load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 14.25 k ? load connected to ground note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx5xx/6xx/7xx ds60001156h-page 406 ? 2009-2013 microchip technology inc. figure 31-28: ejtag timing characteristics t tckeye t tckhigh t tcklow t rf t rf t rf t rf t tsetup t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms table 31-43: ejtag timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +105c for v-temp param. no. symbol description (1) min. max. units conditions ej1 t tckcyc tck cycle time 25 ? ns ? ej2 t tckhigh tck high time 10 ? ns ? ej3 t tcklow tck low time 10 ? ns ? ej4 t tsetup tap signals setup time before rising tck 5?ns ? ej5 t thold tap signals hold time after rising tck 3?ns ? ej6 t tdoout tdo output delay time from falling tck ?5ns ? ej7 t tdozstate tdo 3-state delay time from falling tck ?5ns ? ej8 t trstlow trst low time 25 ? ns ? ej9 t rf tap signals rise/fall time, all input and output ??ns ? note 1: these parameters are characterized, but not tested in manufacturing.
? 2009-2013 microchip technology inc. ds60001156h-page 407 pic32mx5xx/6xx/7xx 32.0 dc and ac device characteristics graphs figure 32-1: v oh ? 4x driver pins figure 32-2: v oh ? 8x driver pins figure 32-3: v ol ? 4x driver pins figure 32-4: v ol ? 8x driver pins note: the graphs provided following this note ar e a statistical summary based on a limited number of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not test ed or guaranteed. in some graphs, the data presented may be out side the specified operating range (e.g., outside specified power supply rang e) and therefore, outsi de the warranted range. -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 ioh(a) voh (v) -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) 3v 3.3v 3.6v absolute maximum -0.080 -0.070 -0.060 -0.050 -0.040 0 030 ioh(a) voh (v) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) v v v a 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 ioh(a) vol (v) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol (v) v v v a 0020 0.030 0.040 0.050 0.060 0.070 0.080 ioh(a) vol (v) 8x 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol (v) 8x v v v a
pic32mx5xx/6xx/7xx ds60001156h-page 408 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 409 pic32mx5xx/6xx/7xx 33.0 packaging information 33.1 package marking information pic32mx575f 512h-80i/pt 0510017 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx575f 512l-80i/pt 0510017 3 e 100-lead tqfp (14x14x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx575f 512l-80i/pf 0510017 3 e
pic32mx5xx/6xx/7xx ds60001156h-page 410 ? 2009-2013 microchip technology inc. 33.1 package marking information (continued) xxxxxxxxxx 64-lead qfn (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx575f example 512h-80i/mr 0510017 3 e xxxxxxxxxx 121-lead tfbga (10x10x1.1 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx575f example 512h-80i/bg 0510017 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e xxxxxxxxxx 124-lead vtla (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx795f example 512l-80i/tl 0510017 3 e
? 2009-2013 microchip technology inc. ds60001156h-page 411 pic32mx5xx/6xx/7xx 33.2 package details the following sections give the technical details of the packages.

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pic32mx5xx/6xx/7xx ds60001156h-page 412 ? 2009-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2013 microchip technology inc. ds60001156h-page 413 pic32mx5xx/6xx/7xx

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pic32mx5xx/6xx/7xx ds60001156h-page 414 ? 2009-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2013 microchip technology inc. ds60001156h-page 415 pic32mx5xx/6xx/7xx

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pic32mx5xx/6xx/7xx ds60001156h-page 416 ? 2009-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2013 microchip technology inc. ds60001156h-page 417 pic32mx5xx/6xx/7xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mx5xx/6xx/7xx ds60001156h-page 418 ? 2009-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2013 microchip technology inc. ds60001156h-page 419 pic32mx5xx/6xx/7xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mx5xx/6xx/7xx ds60001156h-page 420 ? 2009-2013 microchip technology inc.
? 2009-2013 microchip technology inc. ds60001156h-page 421 pic32mx5xx/6xx/7xx
pic32mx5xx/6xx/7xx ds60001156h-page 422 ? 2009-2013 microchip technology inc.
? 2009-2013 microchip technology inc. ds60001156h-page 423 pic32mx5xx/6xx/7xx
pic32mx5xx/6xx/7xx ds60001156h-page 424 ? 2009-2013 microchip technology inc.
? 2009-2013 microchip technology inc. ds60001156h-page 425 pic32mx5xx/6xx/7xx appendix a: migrating from pic32m x3xx/4xx to pic32mx5xx/6xx/7xx devices this appendix provides an overview of considerations for migrating from pic32m x3xx/4xx devices to the pic32mx5xx/6xx/7xx family of devices. the code developed for the pic32mx3xx/4xx devices can be ported to the pic32mx5xx/6xx/7xx devices after making the appropriate changes outlined below. a.1 dma pic32mx5xx/6xx/7xx devices do not support stopping dma transfers in idle mode. a.2 interrupts pic32mx5xx/6xx/7xx devices have persistent interrupts for some of the peripheral modules. this means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. for example, to clear a uart receive interrupt, the user application must first read the uart receive register to clear the interrupt condition and then clear the associated uxif flag to clear the pending uart interrupt. in other words, the uxif flag cannot be cleared by software until t he uart receive register is read. table a-1 outlines the peripherals and associated interrupts that are implemented differently on pic32mx5xx/6xx/7xx versus pic32mx3xx/4xx devices. in addition, on the spi module, the irq numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25. table a-1: pic32mx3xx/4xx versus pic32m x5xx/6xx/7xx interrupt implementation differences module interrupt implementation input capture to clear an interrupt source, read the buffer result (icxbuf) register to obtain the number of capture results in the buffer that are below the interrupt threshold (speci fied by ici<1:0> bits). spi receive and transmit interrupts are controlled by the srxisel<1:0> and stxisel<1:0> bits, respectively. to clear an interrupt source, data mu st be written to, or read from, the spixbuf register to obtain the number of data to rece ive/transmit below the level specified by the srxisel<1:0> and stxisel<1:0> bits. uart tx interrupt will be generated as soon as the uart module is enabled. receive and transmit interrupts are controll ed by the urxisel<1:0> and utxisel<1:0> bits, respectively. to clear an interrupt source, data must be read from, or written to, the uxrxreg or uxtxreg registers to obtain the number of data to receive/transmit below the level specified by the urxisel<1:0> and utxisel<1:0> bits. adc all samples must be read from the result regi sters (adc1bufx) to clear the interrupt source. pmp to clear an interrupt source, read the parallel master port data input/output (pmdin/pmdout) register.
pic32mx5xx/6xx/7xx ds60001156h-page 426 ? 2009-2013 microchip technology inc. appendix b: revision history revision a (august 2009) this is the initial released version of this document. revision b (november 2009) the revision includes the following global update: added note 2 to the shaded table that appears at the beginning of each chapter. this new note provides information regarding the availability of registers and their associated bits. other major changes are referenced by their respective chapter/section in ta b l e b - 1 . table b-1: major section updates section name update description ?high-performance, usb, can and ethernet 32-bit flash microcontrollers? added the following devices: - pic32mx575f256l - pic32mx695f512l - pic32mx695f512h the 100-pin tqfp pin diagrams have been updated to reflect the current pin name locations (see the ?pin diagrams? section). added the 121-pin ball grid array (xbga) pin diagram. updated table 1: ?pic32 usb and can ? features? added the following tables: - table 4: ?pin names: pic 32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pic32mx575f512l devices? - table 5: ?pin names: pic 32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices? - table 6: ?pin names: pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices? updated the following pins as 5v tolerant: - 64-pin qfn: pin 36 (d-/rg3) and pin 37 (d+/rg2) - 64-pin tqfp: pin 36 (d-/rg3) and pin 37 (d+/rg2) - 100-pin tqfp: pin 56 (d-/rg3) and pin 57 (d+/rg2) 1.0 ?guidelines for getting started with 32-bit mi crocontrollers? removed the last sentence of 1.3.1 ?internal regulator mode? . removed section 2.3.2 ?external regulator mode?
? 2009-2013 microchip technology inc. ds60001156h-page 427 pic32mx5xx/6xx/7xx 4.0 ?memory organization? updated all register tables to include the virtual address and all resets columns. updated the title of figure 4-4 to include the pic32mx575f256l device. updated the title of figure 4-6 to include the pic32mx695f512l and pic32mx695f512h devices. also changed pic32mx795f512l to pic32mx795f512 h . updated the title of table 4-3 to include the pic32mx695f512h device. updated the title of table 4-5 to include the pic32mx575f5256l device. updated the title of table 4-6 to include the pic32mx695f512l device. reversed the order of table 4-11 and table 4-12. reversed the order of table 4-14 and table 4-15. updated the title of table 4-15 to include the pic32mx575f256l and pic32mx695f512l devices. updated the title of table 4-45 to include the pic32mx575f256l device. updated the title of table 4-47 to include the pic32mx695f512h and pic32mx695f512l devices. 1.0 ?i/o ports? updated the second paragraph of 1.1.2 ?digital inputs? and removed table 12-1. 22.0 ?10-bit analog-to-digital converter (adc)? updated the adc conversion clock period block diagram (see figure 22-2). 1.0 ?special features? removed references to the envreg pin in 1.3 ?on-chip voltage regulator? . updated the first sentence of 1.3.1 ?on-chip regulator and por? and 1.3.2 ?on-chip regulator and bor? . updated the connections for the on-chip regulator (see figure 1-2). 1.0 ?electrical characteristics? updated the absolute maximum ratings and added note 3. added thermal packaging characteristics for the 121-pin xbga package (see table 1-3). updated the operating current (i dd ) dc characteristics (see table 1-5). updated the idle current (i idle ) dc characteristics (see table 1-6). updated the power-down current (i pd ) dc characteristics (see table 1-7). removed note 1 from the program flas h memory wait state characteristics (see table 1-12). updated the spix module slave mode (cke = 1 ) timing characteristics, changing sp52 to sp35 between the msb and bit 14 on sdox (see figure 1- 13). 1.0 ?packaging information? added the 121-pin xbga package marking information and package details. ?product identification system? added the definition for bg (121-lead 10x10x1.1 mm, xbga). added the definition for speed. table b-1: major section updates (continued) section name update description
pic32mx5xx/6xx/7xx ds60001156h-page 428 ? 2009-2013 microchip technology inc. revision c (february 2010) the revision includes the following updates, as described in table b-2 : table b-2: major section updates section name update description ?high-performance, usb, can and ethernet 32-bit flash microcontrollers? added the following devices: ? pic32mx675f256h ? pic32mx775f256h ? pic32mx775f512h ? pic32mx675f256l ? pic32mx775f256l ? pic32mx775f512l added the following pins: ?erefclk ? ecrsdv ? aerefclk ? aecrsdv added the erefclk and ecrsdv pins to table 5 and table 6. 1.0 ?device overview? updated the pin number pinout i/o descriptions for the following pin names in table 1-1: added the following pins to the pinout i/o descriptions table (table 1-1): ?erefclk ? ecrsdv ? aerefclk ? aecrsdv 4.0 ?memory organization? added new devices and updated the virtual and physical memory map values in figure 4-4. added new devices to figure 4-5. added new devices to the following register maps: ? table 4-3, table 4-4, table 4-6 and table 4-7 (interrupt register maps) ? table 4-12 (i2c2 register map) ? table 4-15 (spi1 register map) ? table 4-24 through table 4-35 (porta-portg register maps) ? table 4-36 and table 4-37 (change notice and pull-up register maps) ? table 4-45 (can1 register map) ? table 4-46 (can2 register map) ? table 4-47 (ethernet cont roller register map) changed the bits named poscmd to poscmod in table 4-42 (device configuration word summary). 1.0 ?special features? changed all references of poscmd to poscmod in the device configuration word 1 register (see register 1-2). appendix a: ?migrating from pic32mx3xx/4xx to pic32mx5xx/6xx/7xx devices? added the new section appendix . ?scl3 ?scl5 ?rtcc ?c1out ?sda3 ?sda5 ?cv ref -?c2in- ?scl2 ?tms ?cv ref +?c2in+ ?sda2 ?tck ?cv refout ?c2out ? scl4 ? tdi ? c1in- ? pma0 ? sda4 ? tdo ? c1in+ ? pma1
? 2009-2013 microchip technology inc. ds60001156h-page 429 pic32mx5xx/6xx/7xx revision d (may 2010) the revision includes the following updates, as described in table b-3 : table b-3: major section updates section name update description ?high-performance, usb, can and ethernet 32-bit flash microcontrollers? updated the initial flash memory range to 64k. updated the initial sram memory range to 16k. added the following devices (see table 1, table 2, table 3 and the pin diagrams): ? pic32mx534f064h ? pic32mx564f064h ? pic32mx664f064h ? pic32mx564f128h ? pic32mx664f128h ? pic32mx764f128h ? pic32mx534f064l ? pic32mx564f064l ? pic32mx664f064l ? pic32mx564f128l ? pic32mx664f128l ? PIC32MX764F128L 4.0 ?memory organization? added new memory maps (figure 4-1, figure 4-2 and figure 4-3). the bit named i2csif was changed to i2c1sif and the bit named i2cbif was changed to i2c1bif in the interrupt register map tables (table 4-2, table 4-3, table 4-4, table 4-5, table 4-6 and table 4-7) added the following devices to the interrupt register map (table 4-2): ? pic32mx534f064h ? pic32mx564f064h ? pic32mx564f128h added the following devices to the interrupt register map (table 4-3): ? pic32mx664f064h ? pic32mx664f128h added the following device to the interrupt register map (table 4-4): ? pic32mx764f128h added the following devices to the interrupt register map (table 4-5): ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l added the following devices to the interrupt register map (table 4-6): ? pic32mx664f064l ? pic32mx664f128l added the following device to the interrupt register map (table 4-7): ? PIC32MX764F128L
pic32mx5xx/6xx/7xx ds60001156h-page 430 ? 2009-2013 microchip technology inc. 4.0 ?memory organization? (continued) made the following bit name changes in the i2c1, i2c3, i2c4 and i2c5 register map (table 4-11): ? i2c3brg sfr: i2c1brg was changed to i2c3brg ? i2c4brg sfr: i2c1brg was changed to i2c4brg ? i2c5brg sfr: i2c1brg was changed to i2c5brg ? i2c4trn sfr: i2ct1data was changed to i2ct2adata ? i2c4rcv sfr: i2cr2data was changed to i2cr2adata ? i2c5trn sfr: i2ct1data was changed to i2ct3adata ? i2c5rcv sfr: i2cr1data was changed to i2cr3adata added the rtsmd bit and uen<1:0> bits to the uart1a, uart1b, uart2a, uart2b, uart3a and uart3b register map (table 4-13) added the sidl bit to the dma global register map (table 4-17). changed the cm bit to cmr in the system control register map (table 4-23). added the following devices to the i2c2, spi1, porta, portc, portd, porte, portf, portg, change notice and pull-up register maps (table 4-12, table 4-14, table 4-24, table 4-27, table 4 -29, table 4-31, table 4-33, table 4-35 and table 4-36): ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l ? pic32mx664f064l ? pic32mx664f128l ? PIC32MX764F128L added the following devices to the po rtc, portd, porte, portf, portg, change notice and pull-up register maps (table 4-26, table 4-28, table 4-30, table 4-32, table 4-34 and table 4-37): ? pic32mx534f064h ? pic32mx564f064h ? pic32mx564f128h ? pic32mx664f064h ? pic32mx664f128h ? pic32mx764f128h added the following devices to the can1 register map (table 4-45): ? pic32mx534f064h ? pic32mx564f064h ? pic32mx564f128h ? pic32mx764f128h ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l ? PIC32MX764F128L added the following devices to the etherne t controller register map (table 4-47): ? pic32mx664f064h ? pic32mx664f128h ? pic32mx764f128h ? pic32mx664f064l ? pic32mx664f128l ? PIC32MX764F128L table b-3: major section updates (continued) section name update description
? 2009-2013 microchip technology inc. ds60001156h-page 431 pic32mx5xx/6xx/7xx 1.0 ?electrical characteristics? updated the typical and maximum dc characteristics: operating current (i dd ) in table 1-5. updated the typical and maximum dc characteristics: idle current (i idle ) in table 1-6. updated the typical and maximum dc characteristics: power-down current (i pd ) in table 1-7. added dc characteristics: program memory parameters d130a and d132a in table 1-11. added the internal voltage referenc e parameter (d305) to the comparator specifications in table 1-13. table b-3: major section updates (continued) section name update description
pic32mx5xx/6xx/7xx ds60001156h-page 432 ? 2009-2013 microchip technology inc. revision e (july 2010) minor corrections were incorporated throughout the document. revision f (december 2010) the revision includes the following global update: v cap /v ddcore has been changed to: v cap /v core other major changes are referenced by their respective chapter/section in ta b l e b - 4 : table b-4: section updates section name update description high-performance, usb, can and ethernet 32-bit flash microcontrollers removed the following analog feature: fv tolerant input pins (digital pins only) updated the term lin 1.2 support as lin support for the peripheral feature: six uart modules with: rs-232, rs-485, and lin support 1.0 ?device overview? updated the value of 64-pin qfn/tqfp pin number for the following pin names: pma0, pma1 and ecrsdv 4.0 ?memory organization? the following register map tables were updated: ? table 4-2: - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8-24/10 to sripl<2:0> in intstat - changed bits 25/9/-24/8 to u5is<1:0> in ipc12 - added note 2 ? table 4-3 through table 4-7: - changed bits 24/8-24/10 to sripl<2:0> in intstat - changed bits 25/9-24/8 to u5is<1:0> in ipc12 ? table 4-3: - changed bits 24/8 to i2c5bif in ifs1 - added note 2 ? table 4-4: - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8 to i2c5bie in iec1 - added note 2 references ? table 4-5: - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8 to i2c5bie in iec1 - added note 2 references ? table 4-6: - changed bit 24/8 to i2c5bif in ifs1 - updated the bit value of bit 24/8 as i2c5bie for the iec1 register. - added note 2 ? table 4-7: - changed bit 25/9 to i2c5sif in ifs1 - changed bit 24/8 as i2c5bif in ifs1 - changed bit 25/9 as i2c5sie in iec1 - changed bit 24/8 as i2c5bie in iec1 - added note 2 references ? added note 2 to table 4-8 ? updated the all resets values for the following registers in table 4-11: i2c3con, i2c4con, i2c5con and i2c1con. ? updated the all resets values for the i2c2con register in table 4-12
? 2009-2013 microchip technology inc. ds60001156h-page 433 pic32mx5xx/6xx/7xx 4.0 ?memory organization? (continued) ? table 4-13: - changed register u4rg to u1brg - changed register u5rg to u3brg - changed register u6rg to u2brg ? table 4-14: - updated the all resets values for the following registers: spi3stat, spi2stat and spi4stat ? table 4-15: updated the all resets values for the spi1stat register ? table 4-17: added note 2 ? table 4-19: added note 2 ? table 4-20: updated the all resets values for the cm1con and cm2con registers ? table 4-21: - updated the all resets values as 0000 for the cvrcon register - updated note 2 ? table 4-38: updated the all resets values for the pmstat register ? table 4-40: updated the all resets values for the checon and chetag registers ? table 4-42: updated the bit value of bit 29/13 as ??? for the devcfg3 register ? table 4-44: - updated the note references in the entire table - changed existing note 1 to note 4 - added notes 1, 2 and 3 - changed bits 23/7 in u1pwrc to uactpnd - changed register u1ddr to u1addr - changed register u4dtp1 to u1bdtp1 - changed register u4dtp2 to u1bdtp2 - changed register u4dtp3 to u1bdtp3 ? table 4-45: - updated the all resets values for the c1con and c1vec registers - changed bits 30/14 in c1con to frz - changed bits 27/11 in c1con to canbusy - changed bits 22/6-16/0 in c1vec to icode<6:0> - changed bits 22/6-16/0 in c1trec to rerrcnt<7:0> - changed bits 31/15-24/8 in c1trec to terrcnt<7:0> ? table 4-46: - updated the all resets values for the c2con and c2vec registers - changed bits 30/14 in c1con to frz - changed bits 27/11 in c1con to canbusy - changed bits 22/6-16/0 in c1vec register to icode<6:0> - changed bits 22/6-16/0 in c1trec register to rerrcnt<7:0> - changed bits 31/15-24/8 in c1trec to terrcnt<7:0> table b-4: section updates (continued) section name update description
pic32mx5xx/6xx/7xx ds60001156h-page 434 ? 2009-2013 microchip technology inc. 7.0 ?interrupt controller? ? updated the following interrupt sources in table 7-1: - changed ic2am ? i2c4 master event to: ic4m ? i2c4 master event - changed ic3am ? i2c5 master event to: ic5m ? i2c4 master event - changed u1e ? uart1a error to: u1e ? uart1 error - changed u4e ? uart1b error to: u4e ? uart4 error - changed u1rx ? uart1a receiver to: u1rx ? uart1 receiver - changed u4rx ? uart1b receiver to: u4rx ? uart4 receiver - changed u1tx ? uart1a transmitter to: u1tx ? uart1 transmitter - changed u4tx ? uart1b transmitter to: u4tx ? uart4 transmitter - changed u6e ? uart2b error to: u6e ? uart6 error - changed u6rx ? uart2b receiver to: u6rx ? uart6 receiver - changed u6tx ? uart2b transmitter to: u6tx ? uart6 transmitter - changed u5e ? uart3b error to: u5e ? uart5 error - changed u5rx ? uart3b receiver to: u5rx ? uart5 receiver - changed u5tx ? uart3b transmitter to: u5tx ? uart5 transmitter 1.0 ?oscillator configuration? updated figure 1-1 1.0 ?output compare? updated figure 1-1 1.0 ?ethernet controller? added a note on using the ethernet controller pins (see note above table 1-3) 1.0 ?comparator voltage reference (cv ref )? updated the note in figure 1-1 1.0 ?special features? updated the bit description for bit 10 in register 1-2 added notes 1 and 2 to register 1-4 1.0 ?electrical characteristics? updated the absolute maximum ratings: ? voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v - 0.3v to +3.6v was updated ? voltage on v bus with respect to v ss - 0.3v to +5.5v was added updated the maximum value of dc16 as 2.1 in table 1-4 updated the typical values for the following parameters: dc20b, dc20c, dc21c, dc22c and dc23c (see table 1-5) updated table 1-11: ? removed the following dc characte ristics: programming temperature 0c ? ta ? +70c (25c recommended) ? updated the minimum value for the parameter number d131 as 2.3 ? removed the conditions for the fo llowing parameter numbers: d130, d131, d132, d135, d136 and d137 ? updated the condition for the parameter number d130a and d132a updated the minimum, typical and maximum values for parameter d305 in table 1-13 added note 2 to table 1-18 updated the minimum and maximum values for parameter f20b (see table 1-19) updated the following figures: ? figure 1-4 ? figure 1-9 ? figure 1-22 ? figure 1-23 appendix a: ?migrating from pic32mx3xx/4xx to pic32mx5xx/ 6xx/7xx devices? removed the a.3 pin assignments sub-section. table b-4: section updates (continued) section name update description
? 2009-2013 microchip technology inc. ds60001156h-page 435 pic32mx5xx/6xx/7xx revision g (may 2011) the revision includes the following global update: ? all references to v ddcore /v cap have been changed to: v core /v cap ? added references to the new v-temp temperature range: -40oc to +105oc this revision also includes minor typographical and formatting changes throughout the data sheet text. major updates are referenced by their respective section in ta b l e b - 5 . table b-5: major section updates section name update description high-performance, usb, can and ethernet 32-bit flash microcontrollers removed the shading for all d- and d+ pins in all pin diagrams. 1.0 ?device overview? updated the v bus description in table 1-1. 1.0 ?guidelines for getting started with 32-bit microcontrollers? added ?alternatively, inputs can be reserved by connecting the pin to vss through a 1k to 10k resistor and configuring the pin as an input.? . 4.0 ?memory organization? added note 3 to the interrupt register map tables (see table 4-2 through ta b l e 4 - 7 . 22.0 ?10-bit analog-to-digital converter (adc)? updated the adc conversion clock period block diagram (see figure 22-2). 1.0 ?comparator voltage reference (cv ref )? updated the comparator voltage reference block diagram (see figure 1-1). 1.0 ?special features? removed the second paragraph from 1.3.1 ?on-chip regulator and por? . 1.0 ?electrical characteristics? added the new v-temp temperature range (-40oc to +105oc) to the heading of all specification tables. updated the ambient temperature u nder bias, updated the voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v, and added voltage on v bus with respect to vss in absolute maximum ratings. added the characteristic, dc5a to operating mips vs. voltage (see table 1-1). updated or added the following parame ters to the operating current (i dd ) dc characteristics: dc20, dc20b, dc23, and dc23b (see table 1- 5). added the following parameters to the idle current (i idle ) dc characteristics: dc30b, dc33b, dc34c, dc35c, and dc36c (see table 1-6). added the following parameters to the power-down current (i pd ) dc characteristics: dc40g, dc40h, dc40i, and dc41g, (see table 1-7). added parameter im51 and note 3 to the i2cx bus data timing requirements (master mode) (see table 1-32). updated the 10-bit adc conversion rate parameters (see table 1-37). updated parameter ad57 (t samp ) in the analog-to-digital conversion timing requirements (see table 1-38). 1.0 ?packaging information? updated the 64-lead plastic quad flat, no lead package (mr) ? 9x9x0.9 mm body [qfn] packing diagram. product identifi cation system added the new v-temp (v) temperature information.
pic32mx5xx/6xx/7xx ds60001156h-page 436 ? 2009-2013 microchip technology inc. revision h (march 2013) this revision includes the following global updates: ? where applicable, control register tables have been added to the document ? all references to v core were removed ? all occurrences of xbga have been updated to: tfbga ? all occurrences of v usb have been updated to: v usb 3 v 3 this revision also includes minor typographical and formatting changes throughout the data sheet text. all other significant changes are referenced by their respective section in table b-6 . table b-6: major section updates section name update description ?32-bit microcontr ollers (up to 512 kb flash and 128 kb sram) with graphics interface, usb, can, and ethernet? updated core features. added the vtla to the packages table. added note 5 to the feature tables (see ta b l e 1 , ta b l e 2 , and ta b l e 3 ). section 2.0 ?guidelines for getting started with 32-bit mcus? the recommended minimum connection was updated (see figure 2-1 ). section 5.0 ?flash program memory? a note regarding flash page size and row size was added. section 8.0 ?oscillator configuration? the r p resistor was added and note 1 wa s updated in the oscillator diagram (see figure 8-1 ). section 31.0 ?electrical characteristics? added note 1 to operating mips vs. voltage (see table 31-1 ). added the vtla package to thermal packaging characteristics (see ta b l e 3 1 - 3 ). added note 2 to dc temperature and voltage specifications (see table 31-4 ). updated note 2 in the operating current dc characteristics (see table 31-5 ). updated note 1 in the idle current dc characteristics (see table 31-6 ). updated note 1 in the power-down current dc characteristics (see table 31-7 ). updated the i/o pin output specifications (see ta b l e 3 1 - 9 ). added note 2 to the bor electrical characteristics (see table 31-10 ). added note 3 to the compar ator specifications (see table 31-13 ). parameter d320 (v core ) was removed (see table 31-15 ). updated the minimum value for parameter os50 (see table 31-18 ). parameter sy01 (t pwrt ) was removed (see table 31-22 ). note 1 was added and the conditions for parameters et3, et4, et7, and et9 were updated in the ethernet module specifications (see table 31-35 ). added note 6 to the adc module specifications (see table 31-36 ). added note 3 to the 10-bit adc conversion rate parameter (see table 31-37 ). added note 4 to the analog-to-digital conversion timing requirements (see table 31-38 ). the following figures were added: ? figure 31-19: ?mdio sourced by the pic32 device? ? figure 31-21: ?transmit signal timing relationships at the mii? ? figure 31-22: ?receive signal timing relationships at the mii?
? 2009-2013 microchip technology inc. ds60001156h-page 437 pic32mx5xx/6xx/7xx section 32.0 ?dc and ac device characteristics graphs? this new chapter was added. section 33.0 ?packaging information? added the 124-lead vtla package information (see section 33.1 ?package marking in formation? and section 33.2 ?package details? ). ?product identification system? added the tl definition for vtla packages. table b-6: major section updates (continued) section name update description
pic32mx5xx/6xx/7xx ds60001156h-page 438 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 439 pic32mx5xx/6xx/7xx index a ac characteristics ............................................................ 374 10-bit conversion rate parameters.......................... 398 adc specifications ................................................... 396 analog-to-digital conversion requirements............. 399 ejtag timing requirements ................................... 406 ethernet .................................................................... 394 internal frc accuracy.............................................. 376 internal rc accuracy ................................................ 377 otg electrical specifications ................................... 405 parallel master port read requirements ................. 403 parallel master port write ......................................... 404 parallel master port write requirements.................. 404 parallel slave port requirements ............................. 402 pll clock timing...................................................... 376 analog-to-digital converter (adc).................................... 247 assembler mpasm assembler................................................... 356 b block diagrams adc1 module............................................................ 247 comparator i/o operating modes............................. 331 comparator voltage reference ................................ 335 connections for on-chip voltage regulator............. 350 core and peripheral modules ..................................... 33 dma .......................................................................... 157 ethernet controller.................................................... 289 i2c circuit ................................................................. 218 input capture ............................................................ 205 interrupt controller .................................................... 131 jtag programming, debugging and trace ports .... 350 mcu............................................................................ 49 output compare module........................................... 209 pic32 can module................................................... 255 pmp pinout and connections to external devices ... 229 prefetch module........................................................ 147 reset system............................................................ 127 rtcc ........................................................................ 237 spi module ............................................................... 211 timer1....................................................................... 197 timer2/3/4/5 (16-bit) ................................................. 201 typical multiplexed port structure ............................ 193 uart ........................................................................ 223 wdt and power-up timer ........................................ 348 brown-out reset (bor) and on-chip voltage regulator................................ 350 c c compilers mplab c18 .............................................................. 356 clock diagram .................................................................. 141 comparator specifications............................................................ 372 comparator module .......................................................... 331 comparator voltage reference (cvref ............................. 335 configuration bits.............................................................. 339 controller area network (can)......................................... 255 cpu module........................................................................ 45 customer change notification service ............................. 443 customer notification service........................................... 443 customer support ............................................................. 443 d dc and ac characteristics graphs and tables ................................................... 407 dc characteristics............................................................ 360 i/o pin input specifications ...................................... 368 i/o pin output specifications.................................... 370 idle current (i idle ) .................................................... 364 power-down current (i pd )........................................ 366 program memory...................................................... 371 temperature and voltage specifications.................. 361 development support ....................................................... 355 direct memory access (dma) controller.......................... 157 e electrical characteristics .................................................. 359 ac............................................................................. 374 errata .................................................................................. 30 ethernet controller............................................................ 289 ethpmm0 (ethernet controller pattern match mask 0)... 296 ethpmm1 (ethernet controller pattern match mask 1)... 296 external clock timer1 timing requirements ................................... 380 timer2, 3, 4, 5 timing requirements ....................... 381 timing requirements ............................................... 375 f flash program memory .................................................... 123 rtsp operation ....................................................... 123 i i/o ports ........................................................................... 193 parallel i/o (pio) ...................................................... 194 input capture .................................................................... 205 instruction set................................................................... 353 inter-integrated circuit (i2c) ............................................. 217 internal voltage reference specifications........................ 373 internet address ............................................................... 443 interrupt controller............................................................ 131 irg, vector and bit location .................................... 132 m mcu architecture overview ................................................ 50 coprocessor 0 registers ............................................ 51 core exception types ................................................ 52 ejtag debug support............................................... 53 power management ................................................... 53 mcu module....................................................................... 49 memory map....................................................................... 60 memory maps ............................................. 56, 57, 58, 59, 61 memory organization ......................................................... 55 layout......................................................................... 55 microchip internet web site.............................................. 443 migration pic32mx3xx/4xx to pic32mx5xx/6xx/7xx......... 425 mplab asm30 assembler, linker, librarian ................... 356 mplab integrated development environment software.. 355 mplab pm3 device programmer .................................... 358 mplab real ice in-circuit emulator system ................ 357 mplink object linker/mplib object librarian ................ 356 o open-drain configuration................................................. 194 oscillator configuration .................................................... 141
pic32mx5xx/6xx/7xx ds60001156h-page 440 ? 2009-2013 microchip technology inc. output compare................................................................ 209 p packaging ......................................................................... 409 details ....................................................................... 411 marking ..................................................................... 409 parallel master port (pmp) ............................................... 229 pic32 family usb interface diagram............................... 174 pinout i/o descriptions (table) ............................................ 34 power-on reset (por) and on-chip voltage regulator ................................ 350 power-saving features..................................................... 337 cpu halted methods ................................................ 337 operation .................................................................. 337 with cpu running..................................................... 337 prefetch cache ................................................................. 147 program flash memory wait state characteristics......................................... 371 r reader response ............................................................. 444 real-time clock and calendar (rtcc)............................ 237 register maps ............................................................. 62?116 registers ad1chs (adc input select) .................................... 253 ad1con1 (adc control 1) ...................................... 249 ad1con2 (adc control 2) ...................................... 251 ad1con3 (adc control 3) ...................................... 252 ad1cssl (adc input scan select) ......................... 254 alrmdate (alarm date value) ............................... 245 alrmtime (alarm time value) ............................... 244 bmxbootsz (boot flash (ifm) size) ..................... 122 bmxcon (bus matrix configuration) ....................... 117 bmxdkpba (data ram kernel program base address) .................................................. 118 bmxdrmsz (data ram size) ................................. 121 bmxdudba (data ram user data base address) . 119 bmxdupba (data ram user program base address) .................................................. 120 bmxpfmsz (program flash (pfm) size) ................ 122 bmxpupba (program flash (pfm) user program base address) .................................................. 121 cheacc (cache access) ........................................ 149 checon (cache control) ........................................ 148 chehit (cache hit statistics) .................................. 154 chelru (cache lru) ............................................. 153 chemis (cache miss statistics) .............................. 154 chemsk (cache tag mask) ................................... 151 chetag (cache tag) ............................................. 150 chew0 (cache word 0)........................................... 151 chew1 (cache word 1)........................................... 152 chew2 (cache word 2)........................................... 152 chew3 (cache word 3)........................................... 153 cicfg (can baud rate configuration).................... 258 cicon (can module control) .................................. 256 cififoba (can message buffer base address) ..... 283 cififocinn (can module message index register ?n?) 288 cififoconn (can fifo control register ?n?)......... 284 cififointn (can fifo interrupt register ?n?) ......... 286 cififouan (can fifo user address register ?n?).. 288 cifltcon0 (can filter control 0)........................... 266 cifltcon1 (can filter control 1)........................... 268 cifltcon2 (can filter control 2)........................... 270 cifltcon3 (can filter control 3)........................... 272 cifltcon4 (can filter control 4) .......................... 274 cifltcon5 (can filter control 5) .......................... 276 cifltcon6 (can filter control 6) .......................... 278 cifltcon7 (can filter control 7) .......................... 280 cifstat (can fifo status).................................... 263 ciint (can interrupt) ............................................... 260 cirxfn (can acceptance filter ?n?)......................... 282 cirxmn (can acceptance filter mask ?n?) .............. 265 cirxovf (can receive fifo overflow status) ..... 264 citmr (can timer) ................................................. 264 citrec (can transmit/receive error count) ......... 263 civec (can interrupt code) .................................... 262 cmstat (comparator control register).................. 333 cmxcon (comparator ?x? control) ........................... 332 cncon (change notice control)............................. 195 cvrcon (comparator voltage reference control) 336 dchxcon (dma channel ?x? control) ..................... 163 dchxcptr (dma channel ?x? cell pointer)............. 170 dchxcsiz (dma channel ?x? cell-size) .................. 170 dchxdat (dma channel ?x? pattern data).............. 171 dchxdptr (channel ?x? destination pointer).......... 169 dchxdsa (dma channel ?x? destination start address)................................................... 167 dchxdsiz (dma channel ?x? destination size)....... 168 dchxecon (dma channel ?x? event control)......... 164 dchxint (dma channel ?x? interrupt control) ......... 165 dchxsptr (dma channel ?x? source pointer)........ 169 dchxssa (dma channel ?x? source start address) 167 dchxssiz (dma channel ?x? source size).............. 168 dcrccon (dma crc control)............................... 160 dcrcdata (dma crc data) ................................. 162 dcrcxor (dma crcxor enable) ....................... 162 ddpcon (debug data port control) ....................... 351 devcfg0 (device configuration word 0................. 340 devcfg1 (device configuration word 1................. 342 devcfg2 (device configuration word 2................. 344 devcfg3 (device configuration word 3................. 346 devid (device and revision id) .............................. 347 dmaaddr (dma address) ...................................... 159 dmacon (dma controller control) ......................... 158 dmastat (dma status) .......................................... 159 emac1cfg1 (ethernet controller mac configuration 1) 313 emac1cfg2 (ethernet controller mac configuration 2) 314 emac1clrt (ethernet controller mac collision win- dow/retry limit)................................................ 318 emac1ipgr (ethernet controller mac non-back-to- back interpacket gap)...................................... 317 emac1ipgt (ethernet controller mac back-to-back in- terpacket gap).................................................. 316 emac1madr (ethernet controller mac mii manage- ment address) .................................................. 324 emac1maxf (ethernet controller mac maximum frame length) .................................................. 319 emac1mcfg (ethernet controller mac mii manage- ment configuration) .......................................... 322 emac1mcmd (ethernet controller mac mii manage- ment command)............................................... 323 emac1mind (ethernet controller mac mii manage- ment indicators)................................................ 326 emac1mrdd (ethernet controller mac mii manage- ment read data) .............................................. 325 emac1mwtd (ethernet controller mac mii manage- ment write data) .............................................. 325
? 2009-2013 microchip technology inc. ds60001156h-page 441 pic32mx5xx/6xx/7xx emac1sa0 (ethernet controller mac station address 0)....................................................................... 327 emac1sa1 (ethernet controller mac station address 1)....................................................................... 328 emac1sa2 (ethernet controller mac station address 2)....................................................................... 329 emac1supp (ethernet controller mac phy support) . 320 emac1test (ethernet controller mac test).......... 321 ethalgnerr (ethernet controller alignment errors statistics) .......................................................... 312 ethcon1 (ethernet controller control 1)................ 291 ethcon2 (ethernet controller control 2)................ 293 ethfcserr (ethernet controller frame check se- quence error statistics) .................................... 311 ethfrmrxok (ethernet controller frames received ok statistics) .................................................... 310 ethfrmtxok (ethernet controller frames transmit- ted ok statistics) .............................................. 307 ethht0 (ethernet controller hash table 0) ............ 295 ethht1 (ethernet controller hash table 1) ............ 295 ethien (ethernet controller interrupt enable)......... 301 ethirq (ethernet controller interrupt request) ...... 302 ethmcolfrm (ethernet controller multiple collision frames statistics) ............................................. 309 ethpm0 (ethernet controller pattern match offset) 297 ethpmcs (ethernet controller pattern match check- sum) .................................................................. 297 ethrxfc (ethernet controller receive filter configura- tion) ................................................................... 298 ethrxovflow (ethernet controller receive overflow statistics) .......................................................... 306 ethrxst (ethernet controller rx packet descriptor start address) ................................................... 294 ethrxwm (ethernet controller receive watermarks) . 300 ethscolfrm (ethernet controller single collision frames statistics) ............................................. 308 ethstat (ethernet controller status)..................... 304 ethtxst (ethernet controller tx packet descriptor start address) ................................................... 294 i2cxcon (i2c control) ............................................. 219 i2cxstat (i2c status) ............................................. 221 icxcon (input capture ?x? control) .......................... 206 iecx (interrupt enable control)................................. 137 ifsx (interrupt flag status)....................................... 137 intcon (interrupt control)....................................... 135 intstat (interrupt status) ....................................... 136 ipcx (interrupt priority control)................................. 138 nvmaddr (flash address) ..................................... 125 nvmcon (programming control) ............................ 124 nvmdata (flash program data)............................. 126 nvmkey (programming unlock).............................. 125 nvmsrcaddr (source data address)................... 126 ocxcon (output compare ?x? control).................... 210 osccon (oscillator control) ................................... 142 osctun (frc tuning) ............................................ 145 pfabt (prefetch cache a bort statistics) ................. 155 pmaddr (parallel port address) ............................. 234 pmaen (parallel port pin enable)............................ 235 pmcon (parallel port control) ................................. 230 pmmode (parallel port mode)................................. 232 pmstat (parallel port status (slave modes only)... 236 rcon (reset control) .............................................. 128 rswrst (software reset) ...................................... 129 rtccon (rtc control)........................................... 238 rtcdate (rtc date value) ................................... 243 rtctime (rtc time value).................................... 242 spixcon (spi control) ............................................ 212 spixstat (spi status) ............................................ 214 t1con (type a timer control)................................ 198 tptmr (temporal proximity timer)......................... 136 txcon (type b timer control) ................................ 203 u1addr (usb address).......................................... 187 u1bdtp1 (usb bdt page 1) .................................. 189 u1bdtp2 (usb bdt page 2) .................................. 190 u1bdtp3 (usb bdt page 3) .................................. 190 u1cnfg1 (usb configuration 1)............................. 191 u1con (usb control).............................................. 185 u1eie (usb error interrupt enable)......................... 183 u1eir (usb error interrupt status).......................... 182 u1ep0-u1ep15 (usb endpoint control) ................. 192 u1frmh (usb frame number high) ...................... 188 u1frml (usb frame number low)........................ 187 u1ie (usb interrupt enable) .................................... 181 u1ir (usb interrupt) ................................................ 180 u1otgcon (usb otg control) ............................. 178 u1otgie (usb otg interrupt enable).................... 176 u1otgir (usb otg interrupt status) .................... 175 u1otgstat (usb otg status) ............................. 177 u1pwrc (usb power control) ............................... 179 u1sof (usb sof threshold) ................................. 189 u1stat (usb status).............................................. 184 u1tok (usb token)................................................ 188 uxmode (uartx mode) ......................................... 225 uxsta (uartx status and control) ........................ 227 wdtcon (watchdog timer control) ....................... 349 resets .............................................................................. 127 revision history................................................................ 426 rtcalrm (rtc alarm control).................................... 240 s serial peripheral interface (spi) ....................................... 211 software simulator (mplab sim) .................................... 357 special features............................................................... 339 t timer1 module.................................................................. 197 timer2/3, timer4/5 modules............................................. 201 timing diagrams 10-bit analog-to-digital conversion (asam = 0, ss- rc<2:0> = 000)................................................ 400 10-bit analog-to-digital conversion (asam = 1, ss- rc<2:0> = 111, samc<4:0> = 00001) ............ 401 can i/o .................................................................... 393 ejtag ...................................................................... 406 external clock .......................................................... 374 i/o characteristics .................................................... 377 i2cx bus data (master mode) .................................. 389 i2cx bus data (slave mode) .................................... 391 i2cx bus start/stop bits (master mode)................... 389 i2cx bus start/stop bits (slave mode)..................... 391 input capture (capx) ............................................... 382 ocx/pwm................................................................. 383 output compare (ocx) ............................................ 382 parallel master port read ........................................ 403 parallel master port write......................................... 404 parallel slave port .................................................... 402 spix master mode (cke = 0) ................................... 384 spix master mode (cke = 1) ................................... 385 spix slave mode (cke = 0) ..................................... 386
pic32mx5xx/6xx/7xx ds60001156h-page 442 ? 2009-2013 microchip technology inc. spix slave mode (cke = 1)...................................... 387 timer1, 2, 3, 4, 5 external clock............................... 380 uart reception ....................................................... 224 uart transmission (8-bit or 9-bit data)................... 224 timing requirements clko and i/o ........................................................... 377 timing specifications can i/o requirements ............................................. 393 i2cx bus data requirements (master mode) ........... 390 i2cx bus data requirements (slave mode) ............. 392 input capture requirements ..................................... 382 output compare requirements ................................ 382 simple ocx/pwm mode requirements.................... 383 spix master mode (cke = 0) requirements ............ 384 spix master mode (cke = 1) requirements ............ 385 spix slave mode (cke = 1) requirements .............. 387 spix slave mode requirements (cke = 0) .............. 386 u uart ................................................................................ 223 usb on-the-go (otg) .................................................... 173 v v cap pin ............................................................................ 350 voltage reference specifications ..................................... 373 voltage regulator (on-chip)............................................. 350 w watchdog timer (wdt) .................................................... 348 www address.................................................................. 443 www, on-line support...................................................... 30
? 2009-2013 microchip technology inc. ds60001156h-page 443 pic32mx5xx/6xx/7xx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic32mx5xx/6xx/7xx ds60001156h-page 444 ? 2009-2013 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds60001156h pic32mx5xx/6xx/7xx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2009-2013 microchip technology inc. ds60001156h-page 445 pic32mx5xx/6xx/7xx product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture mx = 32-bit risc mcu core product groups 5xx = general purpose microcontroller family 6xx = general purpose microcontroller family 7xx = general purpose microcontroller family flash memory family f = flash program memory program memory size 256 = 256k 512 = 512k pin count h = 64-pin l = 100-pin speed 80 = 80 mhz temperature range i = -40c to +85c (industrial) v = -40c to +105c (v-temp) package pt = 64-lead (10x10x1 mm) tqfp (thin quad flatpack) pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pf = 100-lead (14x14x1 mm) tqfp (thin quad flatpack) mr = 64-lead (9x9x0.9 mm) qfn (plastic quad flat) bg = 121-lead (10x10x1.1 mm) tfbga (plastic thin profile ball grid array) tl = 124-lead (9x9x0.9 mm) vtla (very thin leadless array) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample example: pic32mx575f256h-80i/pt: general purpose pic32, 32-bit risc mcu, 256 kb program memory, 64-pin, industrial temperature, tqfp package. microchip brand architecture flash memory family pin count product groups program memory size (kb) pic32 m x 5xx f 512 h t - 80 i / pt - xxx flash memory family speed pattern package temperature range tape and reel flag (if applicable)
pic32mx5xx/6xx/7xx ds60001156h-page 446 ? 2009-2013 microchip technology inc. notes:
? 2009-2013 microchip technology inc. ds60001156h-page 447 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademar ks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2009-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-162077-125-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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